Principal Engineer - Design

Microchip Technology Inc.; Burnaby; On-site; CAD 122,000 - 265,000; Full time

Benefits offered by this job

Health benefits beginning day one

Retirement savings plans

Industry-leading IESPP program

Job summary

Microchip Technology Inc. seeks a Principal Design Engineer to join the ACOV team. You will port SoC RTL to industry-leading HW emulators and FPGA platforms, develop emulation-specific HW for pre-silicon verification, and create a robust test ecosystem across pre/post silicon.

Collaborate with HW, FW, and verification teams to drive system-level co-verification. You will lead debugging of complex embedded real-time systems, apply state-of-the-art protocol analyzers, and report progress with

Qualifications

• BS/MS degree in Electrical/Electronic Engineering or Computer Engineering.
• 10+ years of relevant work experience.
• 5+ years' experience with SAS/SATA/NVMe and thorough knowledge of PCIe.
• Knowledge of Windows/Linux host driver architectures.
• Proficient Linux experience and strong programming/scripting skills (C, Python, Tcl, Bash).
• Proficient in digital design, RTL coding with VHDL/Verilog/SystemVerilog.
• Knowledge of MIPS, ARM, or RISC-V including JTAG, I2C, firmware programming.

Responsibilities

• Port SoC RTL to HW emulators and FPGA platforms.
• Develop emulation specific HW for pre-silicon co-verification.
• Develop common test ecosystem across pre/post silicon.
• Develop FW and tests for pre-silicon subsystem/system level co-verification.
• Troubleshoot complex problems in embedded multi-core RT systems.
• Use protocol analyzers for analysis and error injection.
• Document verification progress and product quality.
• Present technical information to small teams of engineers.

Skills

C/Python scripting

Verilog/VHDL/SystemVerilog

Linux experience

Embedded RTOS concepts

PCIe knowledge

JTAG/I2C protocols

Firmware programming

Education

BS/MS in Electrical/Electronic Engineering or Computer Engineering

Tools

Cadence Palladium/Protium

FPGA platforms

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Job Description

The Architecture Co-Verification team (ACOV) is an exciting, fast paced team responsible for enabling HW/FW development and co-verification of state-of-art System-On-Chip (SoC) devices using industry leading HW emulators (such as Cadence Palladium and Protium).

The team is deployed in all aspects of SoC development phases from architectural exploration to post-silicon validation, HW/FW co-development, pre-silicon functional co-verification, pre/post-silicon performance testing, power analysis, and critical post-silicon investigations.

As a Principal Design Engineer, you will be working closely with hardware designers, firmware engineers, and verification teams throughout the SoC development process. This is a role for a versatile engineer that enjoys the challenges of HW/FW co-development and system level co-verification using leading edge HW emulators and FPGA platforms. It’s a high visibility role that will develop a wide range of skills and exceptional problem-solving ability.

• Porting SoC RTL to industry leading HW emulators and FPGA platforms.
• Developing emulation specific HW for pre-silicon subsystem/system level co-verification.
• Developing common test ecosystem across pre/post silicon.
• Developing FW and tests for pre-silicon subsystem/system level co-verification.
• Troubleshoot and resolve complex problems in embedded multi-core real-time systems executing emulation test plans.
• Utilize state of the art protocol analyzers for analysis and error injection.
• Utilization of test and defect tracking tools to document and report on verification progress and product quality.
• Effectively present technical information to small teams of engineers.

Requirements/Qualifications

• BS/MS degree or higher in Electrical/Electronic Engineering or Computer Engineering.
• 10+ years of relevant work experience.
• 5+ years' experience with one or more serial protocols such as SAS/SATA/NVMe and a thorough knowledge of PCIe.
• Knowledge of key components of a server and storage solution including Windows/Linux host driver architectures.
• Willing to learn in a fast-paced environment, and being an organized self-starter.
• Proficient Linux experience and strong programming/scripting skills with languages such as C, Python, Tcl and Bash.
• Proficient in digital design, RTL coding with VHDL, Verilog, or System Verilog experience.
• Creation & management of system validation testing schedules and their execution.
• Knowledge of MIPS, ARM, or RISC-V architecture, including JTAG, I2C, and firmware programming.

Desired Skills

• Excellent analytical and documentation skills.
• Strong problem solving, communication and interpersonal skills are required.
• Ability to quickly learn new technologies.
• Highly motivated team player who sets personal goals and achieves those goals without supervision.
• Experience with RAID HBA’s, SAS Controllers and their associated Software Testing Strategies in an asset.
• Experience with test automation, testing methodologies, and test tools
• Isolation and resolution of complex software & firmware problems in embedded real-time systems.
• Troubleshoot and resolve complex problems in embedded multi-core real-time systems.
• Knowledge of Embedded Linux development as well as RTOS constructs including processes, threads, scheduling, synchronization mechanisms, memory management.
• Cadence infrastructure support and process flows is an asset.

Travel Time

0% - 25%

Pay Range

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature. Find more information about all our benefits at the link below:

Benefits of working at Microchip

The annual base salary range for this position is $86,000 - $186,000.*

• Range is dependent on numerous factors including job location, skills and experience.