Physical Design Engineer II (PNR/Physical Verification/STA/EMIR)

Kibbi Technologies Inc.; Toronto; On-site; CAD 90,000 - 130,000; Full time

Job summary

Cadence is seeking a skilled Physical Design Engineer to join our team in Toronto. You will participate in or lead next‑generation physical design, methodology, and flow development across advanced technology nodes.

The role involves floor planning, power grid design, place and route, clock tree synthesis, timing closure, and signoffs, collaborating with RTL and analog teams to ensure successful tapeouts.

Qualifications

• Bachelor or above in EE/CS/IT with 3+ years of experience.
• Extensive knowledge of the design rule for the process of N7/N5 and below.
• Experience with DRC/LVS/ANT etc. in physical design is a plus.

Responsibilities

• Lead or participate in next‑generation physical design, methodology, and flow development.
• Perform physical design implementation: floorplanning, clock tree synthesis, timing closure.
• Collaborate with RTL and Analog teams to ensure successful tapeouts.

Skills

Static timing analysis

Physical design

Floor planning

Scripting languages

Education

Bachelor's degree in EE/CS/IT

Tools

Cadence tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. As well as participating in or leading next generation PHY IP physical design, methodology and flow development, the candidate will work closely with our RTL design team & Analog Team to ensure successful tapeouts.

Main Job Tasks And Responsibilities

• Participating in or leading next‑generation physical design, methodology, and flow development in advanced technology nodes.
• Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.

Position Requirements

• Bachelor or above degree in majors of EE/CS/IT, with 3+ years work experience
• Extensive knowledge of the design rule for the process of N7/N5 and below
• Knowledge of scripting languages and use in methodology
• Ability of fixing the physical design violations, including: DRC, DFM, LVS, ANT, ERC etc.
• Deep experience of static timing analysis
• Ability to learn quickly
• High level of communication and teamwork
• Carefulness, responsibility, and persistence

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We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.