Design Engineer II

Cadence Design Systems; Montreal (administrative region); Hybrid; CAD 74,000 - 137,000; Full time

Benefits offered by this job

RRSP participation

TFSA/retirement savings

Life insurance

Health coverage with dental/vision

Stock Purchase Plan

Job summary

Cadence Design Systems is seeking a Design Engineer II to join a dynamic team in Montreal, Ottawa, and Toronto. The role focuses on verification of digital RTL and development of reusable verification environments within a high-performance IP context. Collaboration across design, verification, and project management teams across global sites is essential.

The candidate should have a B.S. in EE/CPE/CSC, strong SV/UVM knowledge, and experience with scripting (Python).

Qualifications

• Bachelor of Science in Electrical/Computer Engineering or Computer Science.
• Understanding of verification architecture and methodologies.
• Understanding of Metric Driven Verification and Universal Verification Methodologies.
• Knowledge of SystemVerilog Assertions (SVAs) and digital design flow.

Responsibilities

• Verify digital RTL and develop reusable verification components/environments.
• Contribute to verification flow development, test plan execution, and coverage closure.
• Communicate progress effectively with cross-functional teams across multiple geographies.
• Collaborate with design, verification, project management, and analog/digital design groups.

Skills

RTL verification

SV/UVM fundamentals

Python scripting

Communication skills

Education

Bachelor of Science in Electrical/Computer Engineering or Computer Science

Tools

Cadence tools

SystemVerilog

Job description

Job Title & Location

Design Engineer II

Montreal, Ottawa, Toronto

Overview

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This role is for an existing vacancy. Job Title: Design Engineer II Location: Montreal, Ottawa, Toronto Overview This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols. The successful candidate will be a highly motivated self-starter who is able to work independently to complete assigned tasks within required project timelines with high quality.

Responsibilities

• The candidate will primarily be responsible for the verification of digital RTL and development of re-usable verification components and environments.
• It is also expected that the candidate will contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure.
• The ideal candidate will have a fundamental understanding of the end-to-end verification flow in order to accurately and efficiently communicate with all members of the technical staff regarding overall project development progress and status.
• The most successful candidates will be able to demonstrate excellent command of fundamental logic principles as well as excellent problem solving and communication skills.
• The candidate should be able to work as part of a small and focused team of engineers and be able to collaborate successfully as needed with design teams, verification teams, project management, and digital and analog design teams in multiple worldwide geographies.
• The Candidate should be willing to work full time in the Montreal, Quebec, Canada office and be willing to travel as required by job function (expectation is 5% travel or less).

Required Qualifications

• Bachelor of Science in Electrical(EE)/Computer Engineering (CPE) or Computer Science (CSC)
• Understanding of verification architecture and methodologies
• Understanding of Metric Driven Verification
• Understanding of Universal Verification Methodologies
• Understanding of the identification, planning and creation of functional coverage and checks
• Understanding of System Verilog Assertions (SVAs)
• Understanding of digital design flow

Preferred Qualifications

• Master of Science in EE/CPE/CSC
• Experience with SystemVerilog UVM coding language is desired
• Experience with scripting languages such as Python, Perl, Ruby, Sed, or Awk is also strongly preferred
• Exposure to Standard Protocol knowledge for any of the following areas: PCIe, USB, SATA, Ethernet, Display Port, HDMI
• Exposure to Formal Verification Technologies
• Exposure to Mixed Signal Design experience
• Experience with Cadence tools experience
• Exposure to Low Power verification experience using CPF or UPF

Salary

The annual salary range for MOUNT-ROYAL (Montreal)is 73,500.00 - 136,500.00 CAD Annual. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

Benefits

• paid vacation and holidays
• leave of absence programs
• Registered Retirement Savings Plan (RRSP)
• Tax Free Savings (TFSA) plan for post-tax investment savings
• Employee Stock Purchase Plan
• group health coverage that includes dental, vision and Emotional Wellbeing Support (EAP) benefits for you and your eligible dependents
• Cadence also offers employee and dependent Life insurance, and short-term and long-term disability
• In addition, Cadence provides Global Travel Medical coverage, Business Travel Accident Insurance, and a funded Lifestyle Spending Account (LSA)

French Title & Location

Ingénieur de conception II

Montreal, Ottawa, Toronto

French Description

Cadence Design Systems est à la recherche de candidats d’excellence pour joindre une équipe expérimentée et dynamique d’ingénieurs en charge du développement d’IP au service des standards de l’industrie.

Le candidat sélectionné aura la charge de la vérification de modules numériques RTL et du développement de modules de vérification réutilisables.

Le candidat sera aussi amené à contribuer à toutes les phases du processus de vérification : élaboration du plan de vérification, codage des points de couverture, génération de stimuli et analyse de couverture.

Le candidat devra posséder des connaissances de base des méthodes de design et de vérification des composantes numériques.

Le candidat devra être autonome, dynamique et démontrer de très bonnes qualités de communication.

Le groupe de design IP est une équipe multidisciplinaire composée d’ingénieurs provenant de divers sites à travers le monde.

Faisant parti du groupe de vérification, le candidat sera amené à collaborer avec diverses disciplines et phases de la réalisation complète d’IP matériel : design numérique et analogique, design physique, production, etc.

Le groupe de design IP est une organisation grandissante.

Le catalogue complet se trouve au site suivant : http://ip.cadence.com/ipportfolio/ip-portfolio-overview.

French Required Experience

• Baccalauréat en Ingénierie électrique, sciences appliquées ou domaine connexe.
• Compréhension des principes de base de la vérification de composantes numériques.
• Compréhension de base des vérifications basées sur les métriques (Metric Driven Verification).
• Connaissance des Méthodes de Vérification Universelles (UVM).
• Connaissance du langage d’assertions SystemVerilog (SVAs).
• Compréhension de base du flot de design numérique.

French Preferred Experience

• Maîtrise en génie électrique, sciences appliquées ou domaine connexe.
• Expérience avec le langage de vérification SystemVerilog UVM.
• Expérience avec différents langages de script tel que Python, Perl, Ruby, etc.
• Connaissance de base des protocoles de transfert de données tel que PCIe, USB, SATA, Ethernet, Display Port, HDMI.
• Connaissance de base des techniques de vérification formelle.
• Connaissance de base des composantes mixtes (analogiques/numériques).

Equal Opportunity Policy

Cadence est une employeuse qui souscrit à l’égalité des chances et qui s’engage à embaucher une main-d'oeuvre diversifiée.

We welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.

Additional Jobs Equal Employment Opportunity Policy: Cadence is committed to equal employment opportunity throughout all levels of the organization.

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Cadence plays a critical role in creating the technologies that modern life depends on.

We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For.

Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer.

All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.