PCIe RTL Design Engineer — Hybrid (Vancouver)

AMD; Vancouver; Hybrid; CAD 120,000 - 160,000; Full time

Job summary

AMD in Vancouver is seeking a Digital Design Engineer to help develop PCIe IP for server, client, GPU products. You will contribute to RTL design, architecture definitions, and bring-up from concept to silicon, collaborating with a global team.

The role emphasizes timing, power, verification collaboration, and adherence to design methodologies. A strong background in Verilog/SystemVerilog and multi-clock domains helps.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Engineering Science, or a related field.
• Master's degree preferred.
• Experience in ASIC/SoC digital design and RTL development.

Responsibilities

• Design and develop RTL for AMD's PCI Express (PCIe) IP used across next-generation server, client, GPU, and semi-custom products.
• Partner with architects and design teams to define and implement innovative microarchitectural features.
• Drive high-quality RTL development with focus on timing closure, CDC analysis, lint compliance, and overall design robustness.
• Implement and optimize low-power design techniques while maintaining performance and functionality targets.
• Collaborate with verification engineers to support simulation, debug, validation, and issue resolution throughout the project lifecycle.
• Participate in silicon bring-up activities and contribute to debugging post-silicon and customer-reported issues.
• Support design reviews and continuously improve design methodologies and development processes.

Skills

Verilog/SystemVerilog

RTL design

Timing analysis

CDC analysis

Lint

Low-power design

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Engineering Science, or a related field

Master's degree preferred

Tools

Logic analyzers

Oscilloscopes

Lab equipment

Job description

AMD in Vancouver is seeking a Digital Design Engineer to help develop PCIe IP for server, client, GPU products. You will contribute to RTL design, architecture definitions, and bring-up from concept to silicon, collaborating with a global team.

The role emphasizes timing, power, verification collaboration, and adherence to design methodologies. A strong background in Verilog/SystemVerilog and multi-clock domains helps.