IOHUB Design Verification Engineer – ASIC/SoC Expert

Advanced Micro Devices, Inc.; Markham; Híbrido; CAD 90 000 - 140 000; Tempo integral

Resumo da oferta

Advanced Micro Devices, Inc. is seeking a skilled verification engineer to lead IOHUB verification efforts for the NBIO IP in a global, cross-functional environment.

The role requires strong experience in IP/SoC verification, UVM, and SystemVerilog, with a track record of delivering verification components and driving closure. The successful candidate will collaborate with silicon design engineers and architecture teams, ensuring precise validation of complex IP across multiple sites.

Qualificações

• Master’s or Bachelor’s degree with digital ASIC or SoC verification experience.
• Strong knowledge of UVM, Verilog, SystemC and SystemVerilog.
• Experience with IP/SoC verification of complex IP/ASIC/SoC.
• Fluency in English.

Responsabilidades

• Define the IOHUB verification strategy and scope.
• Develop the IOHUB test plan, implement DRVR, and drive verification closure.
• Work closely with the Design and Architecture teams to develop new verification components.
• Organize and attend conference calls with global teams for strategy alignment, status synchronization, and related activities.

Conhecimentos

English fluency

IP/SoC verification

UVM

Verilog

SystemVerilog

SystemC

PSL/SVA

Constrained-random

Verification planning

Virtualization

AI assistants

Collaboration

Formação académica

Master’s degree in electrical engineering and digital ASIC or SoC design verification experience

Bachelor’s degree in electrical engineering and digital ASIC or SoC design verification experience

Ferramentas

UVM

Descrição da oferta de emprego

Advanced Micro Devices, Inc. is seeking a skilled verification engineer to lead IOHUB verification efforts for the NBIO IP in a global, cross-functional environment.

The role requires strong experience in IP/SoC verification, UVM, and SystemVerilog, with a track record of delivering verification components and driving closure. The successful candidate will collaborate with silicon design engineers and architecture teams, ensuring precise validation of complex IP across multiple sites.