IOHUB Design Verification Engineer

Advanced Micro Devices, Inc.; Markham; Hybrid; CAD 90,000 - 140,000; Full time

Job summary

Advanced Micro Devices, Inc. is seeking a skilled verification engineer to lead IOHUB verification efforts for the NBIO IP in a global, cross-functional environment.

The role requires strong experience in IP/SoC verification, UVM, and SystemVerilog, with a track record of delivering verification components and driving closure. The successful candidate will collaborate with silicon design engineers and architecture teams, ensuring precise validation of complex IP across multiple sites.

Qualifications

• Master’s or Bachelor’s degree with digital ASIC or SoC verification experience.
• Strong knowledge of UVM, Verilog, SystemC and SystemVerilog.
• Experience with IP/SoC verification of complex IP/ASIC/SoC.
• Fluency in English.

Responsibilities

• Define the IOHUB verification strategy and scope.
• Develop the IOHUB test plan, implement DRVR, and drive verification closure.
• Work closely with the Design and Architecture teams to develop new verification components.
• Organize and attend conference calls with global teams for strategy alignment, status synchronization, and related activities.

Skills

English fluency

IP/SoC verification

UVM

Verilog

SystemVerilog

SystemC

PSL/SVA

Constrained-random

Verification planning

Virtualization

AI assistants

Collaboration

Education

Master’s degree in electrical engineering and digital ASIC or SoC design verification experience

Bachelor’s degree in electrical engineering and digital ASIC or SoC design verification experience

Tools

UVM

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re redesigning next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger— technology that moves the world forward. Join us and, together, we’ll advance your career.

The Role

The AMD NBIO (North Bridge I/O) team delivers industry-leading, high-performance interconnect IP for AMD products, including discrete GPUs, machine learning products, APUs, servers, and game consoles. The global NBIO organization operates seamlessly across China, North America, and Europe.

IOHUB sits at the center of the system’s data paths. It includes two foundational IP blocks, IOHUB Core and IOMMU, as well as the IOHUB. IOHUB Core is the system’s PCI host bridge and provides decoding and routing services to PCIe and other devices. The IOMMU (I/O Memory Management Unit) is responsible for address translation and memory protection. It plays a critical role in I/O virtualization technology, which is widely used in hyperscale data centers.

The Person

The successful candidate will work closely with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, with strong communication and problem‑solving skills.

• Demonstrates strong teamwork
• Drives work through completion

Key Responsibilities

• Define the IOHUB verification strategy and scope.
• Develop the IOHUB test plan, implement DRVR, and drive verification closure.
• Work closely with the Design and Architecture teams to develop new verification components.
• Organize and attend conference calls with global teams for strategy alignment, status synchronization, and related activities.

Preferred Experience

• Experience working in a global company and fluency in spoken English.
• Experience with complex IP, ASIC, or SoC design verification. Direct experience with IP/SoC development, processors such as CPUs or GPUs, or industry bus standards such as PCIe or HT is preferred.
• Good knowledge of UVM, Verilog, SystemC, and SystemVerilog.
• Solid knowledge of hardware verification methodologies, including coverage-based verification, hardware assertions such as PSL or SVA, and constrained-random techniques.
• Experience with verification planning is an asset.
• Knowledge of virtualization is an asset.
• Experience developing with AI assistants is a plus.
• Strong collaboration skills.

Academic Credentials

• Master’s degree in electrical engineering and digital ASIC or SoC design verification experience, or
• Bachelor’s degree in electrical engineering and digital ASIC or SoC design verification experience.

Location:

Markham, ON or Vancouver, BC

#LI-MO2

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.