Lead ASIC Design Engineer — AI-Optimized SoC IP

AMD; Markham; On-site; CAD 130,000 - 180,000; Full time

Job summary

AMD's IOHUB team is seeking a Principal ASIC Design Engineer to provide technical leadership for next-generation IP development across server, data center, client, and embedded markets. You will shape architectures, mentor engineers, and drive design strategies that enable AI-driven data movement and high-performance silicon.

As a senior technologist, you will collaborate with architecture, verification, firmware, and product teams to turn requirements into robust silicon solutions, uphold

Qualifications

• Bachelor's degree in Electrical Engineering or related field is required.
• Demonstrated leadership in ASIC/silicon design and multiple tape-outs preferred.
• Strong proficiency in RTL design, microarchitecture, and IP development.

Responsibilities

• Provide technical leadership for IOHUB IP development from architecture through tape-out and post-silicon validation.
• Collaborate with architecture teams to translate product objectives into scalable design solutions.
• Drive design quality, timing, area, power, security, and reliability goals.
• Lead cross-functional collaboration across architecture, design, verification, firmware, physical design, and product teams.
• Mentor engineers through architecture reviews, implementation challenges, and debugging.
• Drive post-silicon bring-up, validation, and root-cause analysis to improve quality.

Skills

RTL design

Microarchitecture

SoC design

Verilog

SystemVerilog

Python

Perl

Tcl

Leadership

Communication

AI tools

Education

Bachelor's degree in Electrical Engineering

Master's degree or Ph.D. in related field

Tools

Verilog simulators

Static analysis tools

Synthesis tools

Formal verification tools

Job description

AMD's IOHUB team is seeking a Principal ASIC Design Engineer to provide technical leadership for next-generation IP development across server, data center, client, and embedded markets. You will shape architectures, mentor engineers, and drive design strategies that enable AI-driven data movement and high-performance silicon.

As a senior technologist, you will collaborate with architecture, verification, firmware, and product teams to turn requirements into robust silicon solutions, uphold