Design Verification Lead - PCIe/CXL IP Expert

AMD; Markham; Sur place; CAD 140 000 - 190 000; Plein temps

Résumé du poste

AMD in Markham, ON is seeking a Design Verification Engineer Lead to drive front-end verification for FPGA and ASIC IP, delivering first-pass silicon for PCIe and CXL solutions. You will collaborate with architecture, IP, physical design, firmware and product engineering teams to ensure robust verification across the full development lifecycle.

Lead the verification effort, build UVM environments, develop directed and constrained randomness tests, run regressions, debug failures, and push

Qualifications

• Bachelor's or Master's in Electrical/Computer Engineering, CS or related field.
• Experience in ASIC/IP verification using UVM.
• Strong SystemVerilog/Verilog and object-oriented programming skills.
• Experience with PCIe, CXL, Ethernet protocols.

Responsabilités

• Collaborate with architects, hardware designers, and firmware teams to verify PCIe, CXL, and high-speed connectivity features.
• Develop verification plans addressing feature interactions and system use cases.
• Build IP or subsystem-level UVM environments with monitors and scoreboards.
• Create directed and constrained-random tests, run regressions, and debug to improve coverage.
• Drive verification automation and AI-assisted tooling adoption.

Connaissances

UVM verification

SystemVerilog

Verilog

Object-oriented programming

UVM-based verification

PCIe

CXL

Ethernet

PCIe Gen6

Python

Perl

ASIC/FPGA lifecycle

Performance verification

HLS tools

Verification efficiency

Technical leadership

Mentoring

Distributed teamwork

Computer architecture

Formation

Bachelor's or Master's in Electrical/Computer Engineering or CS

Description du poste

AMD in Markham, ON is seeking a Design Verification Engineer Lead to drive front-end verification for FPGA and ASIC IP, delivering first-pass silicon for PCIe and CXL solutions. You will collaborate with architecture, IP, physical design, firmware and product engineering teams to ensure robust verification across the full development lifecycle.

Lead the verification effort, build UVM environments, develop directed and constrained randomness tests, run regressions, debug failures, and push