Design Verification Engineer (PCIe)

HCLTech; Canada; On-site; CAD 90,000 - 130,000; Full time

Job summary

HCL Technologies Limited is seeking a Design Verification Engineer to join our semiconductor verification team in Canada. You will design and develop robust SV/UVM-based verification environments, verify PCIe Gen3/Gen4/Gen5 protocols, and contribute to reusable testbenches and methodologies.

You should be proficient in SVA, coverage-driven verification, and constrained-random testing, with experience using simulators such as VCS, Xcelium, or Questa.

Qualifications

• Strong experience in SystemVerilog and UVM for verification.
• Hands-on PCIe Gen3/Gen4/Gen5 protocol verification.
• Design verification environments, testbenches, and methodologies.
• Experience with assertions (SVA) and coverage models.

Responsibilities

• Design and develop robust verification environments using SystemVerilog and UVM.
• Verify PCIe Gen3/Gen4/Gen5 protocols and ensure compliance with specifications.
• Develop reusable verification components, testbenches, and methodologies.
• Create and maintain assertions (SVA), coverage models, and constrained-random test scenarios.
• Debug complex design and protocol issues and drive them to closure.
• Collaborate closely with design and architecture teams.

Skills

SystemVerilog

UVM

PCIe verification

Testbench development

SVA/coverage-driven verification

Constrained-random verification

Debugging/analytical

Tools

VCS

Xcelium

Questa

VIPs

Job description

Are you passionate about cutting-edge semiconductor and high-speed interface technologies? We are looking for a Design Verification (DV) Engineer with strong expertise in SystemVerilog (SV), UVM, and PCIe verification to join a dynamic engineering team.

Key Responsibilities:

• Design and develop robust verification environments using SystemVerilog and UVM
• Verify PCIe Gen3/Gen4/Gen5 protocols and ensure compliance with specifications
• Develop reusable verification components, testbenches, and methodologies
• Create and maintain assertions (SVA), coverage models, and constrained-random test scenarios
• Debug complex design and protocol issues and drive them to closure
• Collaborate closely with design and architecture teams

Required Skills:

• Strong experience in Design Verification using SystemVerilog (SV) and UVM
• Hands-on experience in PCIe Gen3/Gen4/Gen5 protocol verification
• Strong understanding of:
• LTSSM
• Data Link Layer
• Physical Layer
• Exposure to AXI, APB, and AHB protocols
• Experience developing reusable verification environments and VIPs
• Knowledge of SVA, coverage-driven verification, and constrained-random methodologies
• Experience with simulators such as VCS, Xcelium, or Questa
• Excellent debugging, analytical, and problem-solving skills