Design Verification Engineer

Diligent Tec, Inc; Vancouver; Hybrid; CAD 83,000 - 124,000; Full time

Job summary

NeurealM/ Microchip in Vancouver, BC is seeking a Design Verification Engineer to develop and execute verification environments for ASIC/SoC designs.

You will build SystemVerilog/UVM testbenches, run functional, regression, and constrained-random tests, and push coverage closure. You will debug RTL and simulate issues with the design team, and verify AMBA/AXI, PCIe, Ethernet interfaces. This contract role starts with one month hybrid work in Vancouver, then transitions to remote work.

Qualifications

• Strong SystemVerilog and UVM experience.
• Solid RTL and digital design knowledge with ASIC/SoC verification.
• Experience with VCS, Xcelium, or Questa simulation tools.
• Strong debugging and scripting skills.
• Bachelor's/Master's degree in Electrical, Electronics, or Computer Engineering.

Responsibilities

• Develop verification environments and testbenches using SystemVerilog and UVM.
• Create functional, regression, and constrained-random tests.
• Analyze functional and code coverage and drive closure.
• Debug RTL and simulation issues and work with design teams to resolve issues.
• Verify protocols such as AMBA/AXI, PCIe, Ethernet, or similar interfaces.
• Automate testing and regression using Python, Perl, or Shell scripting.

Skills

SystemVerilog

UVM

RTL

ASIC verification

Debugging

Python scripting

Perl scripting

Shell scripting

Education

Bachelors/Masters in Electrical/Computer Eng

Tools

VCS

Xcelium

Questa

Job description

Job Title: Design Verification Engineer

Client: NeurealM/ Microchip

Location: Vancouver, BC, Canada - Initial 1 month Hybrid then after Remote

Job Type: Contract

Job Summary

We are looking for aDesign Verification Engineerwith strong experience inASIC/SoC verificationto develop and execute verification environments and ensure high-quality digital designs.

Responsibilities

• Develop verification environments and testbenches usingSystemVerilog and UVM.
• Create and execute functional, regression, and constrained-random tests.
• Analyzefunctional/code coverageand drive coverage closure.
• Debug RTL and simulation failures and work with design teams to resolve issues.
• Verify protocols such asAMBA/AXI, PCIe, Ethernet, or similar interfaces.
• Automate testing and regression usingPython, Perl, or Shell scripting.

Required Skills

• StrongSystemVerilog & UVMexperience.
• Solid understanding ofRTL, digital design, and ASIC/SoC verification.
• Experience with simulation tools such asVCS, Xcelium, or Questa.
• Strong debugging and scripting skills.
• Bachelor's/Master's degree inElectrical, Electronics, or Computer Engineering.