Design Verification Engineer

AMD; Vancouver; On-site; CAD 90,000 - 130,000; Full time

Job summary

AMD is seeking an experienced Design Verification Engineer to join our Vancouver team. You will verify PCIe IP and subsystems using SystemVerilog and UVM, collaborate with architecture, design, and validation teams, and drive verification strategies to ensure silicon success.

The role provides broad exposure to the ASIC development lifecycle, from RTL to signoff, in a fast-paced, collaborative environment with cross-functional teams and state-of-the-art tools.

Qualifications

• Strong experience with SystemVerilog and UVM-based verification methodologies.
• Experience developing verification environments, testbench architectures, and reusable verification components.
• Knowledge of RTL design concepts and Verilog HDL.
• Experience with ASIC or SoC verification flows.
• Programming experience with C/C++, Java, or other object-oriented languages.
• Scripting experience using Perl, Python, Ruby, Shell, or similar languages in Linux/UNIX environments.
• Experience with industry-standard simulators and debug tools such as VCS, Xcelium/NCSIM, Questa, and Verdi.
• Knowledge of PCI Express (PCIe) architecture and protocols.
• Understanding of processor and system architectures, including x86 and ARM.
• Experience with on-chip interconnects and industry-standard interfaces such as AXI and PIPE.

Responsibilities

• Develop, review, and execute comprehensive verification plans to ensure feature and functional coverage.
• Design and implement scalable verification environments using SystemVerilog and UVM.
• Develop reusable verification components, including UVCs, BFMs, models, monitors, and checkers.
• Create, maintain, and execute constrained-random and directed test suites.
• Analyze functional, code, and assertion coverage metrics and drive coverage closure.
• Develop assertions, scoreboards, and other verification infrastructure to improve design quality.
• Debug simulation failures and regression issues to identify root causes and drive resolution.
• Reproduce and analyze silicon-reported functional issues within simulation environments.
• Leverage internal and third-party EDA/CAD tools to support verification development and execution.
• Participate in code reviews and verification signoff activities.
• Collaborate with design, architecture, and validation teams throughout the product development cycle.
• Provide technical leadership by driving verification projects from planning through signoff.

Skills

SystemVerilog/UVM

Verification environments

RTL concepts

ASIC/SoC verification

C/C++/Java

Scripting languages

Simulation tools

PCIe architecture

Processor architectures

On-chip interfaces

Education

Masters or bachelor in electrical or computer engineering

Tools

VCS

Xcelium/NCSIM

Questa

Verdi

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we'll advance your career.

The Role

AMD is seeking an experienced Design Verification Engineer to join our team developing next-generation high-performance computing and semiconductor products. In this role, you will be responsible for verifying complex PCI Express (PCIe) IP and subsystem designs using industry-leading verification methodologies, including SystemVerilog and UVM. You will collaborate closely with architecture, design, and validation teams to develop comprehensive verification strategies, drive coverage closure, and ensure first-pass silicon success. This position provides broad exposure to the ASIC development lifecycle, from architectural definition and RTL development through verification signoff and silicon bring-up. The ideal candidate is passionate about solving challenging technical problems, improving verification efficiency, and delivering high-quality designs in a fast-paced, collaborative environment.

The Person

• Strong experience with SystemVerilog and UVM-based verification methodologies.
• Experience developing verification environments, testbench architectures, and reusable verification components.
• Knowledge of RTL design concepts and Verilog HDL.
• Experience with ASIC or SoC verification flows.
• Programming experience with C/C++, Java, or other object-oriented languages.
• Scripting experience using Perl, Python, Ruby, Shell, or similar languages in Linux/UNIX environments.
• Experience with industry-standard simulators and debug tools such as VCS, Xcelium/NCSIM, Questa, and Verdi.
• Knowledge of PCI Express (PCIe) architecture and protocols.
• Understanding of processor and system architectures, including x86 and ARM.
• Experience with on-chip interconnects and industry-standard interfaces such as AXI and PIPE.

Key Responsibilities

• Develop, review, and execute comprehensive verification plans to ensure feature and functional coverage.
• Design and implement scalable verification environments using SystemVerilog and UVM.
• Develop reusable verification components, including UVCs, BFMs, models, monitors, and checkers.
• Create, maintain, and execute constrained-random and directed test suites.
• Analyze functional, code, and assertion coverage metrics and drive coverage closure.
• Develop assertions, scoreboards, and other verification infrastructure to improve design quality.
• Debug simulation failures and regression issues to identify root causes and drive resolution.
• Reproduce and analyze silicon-reported functional issues within simulation environments.
• Leverage internal and third-party EDA/CAD tools to support verification development and execution.
• Participate in code reviews and verification signoff activities.
• Collaborate with design, architecture, and validation teams throughout the product development cycle.
• Provide technical leadership by driving verification projects from planning through signoff.

Preferred Experience

• Strong experience with SystemVerilog and UVM-based verification methodologies.
• Experience developing verification environments, testbench architectures, and reusable verification components.
• Knowledge of RTL design concepts and Verilog HDL.
• Experience with ASIC or SoC verification flows.
• Programming experience with C/C++, Java, or other object-oriented languages.
• Scripting experience using Perl, Python, Ruby, Shell, or similar languages in Linux/UNIX environments.
• Experience with industry-standard simulators and debug tools such as VCS, Xcelium/NCSIM, Questa, and Verdi.
• Knowledge of PCI Express (PCIe) architecture and protocols.
• Understanding of processor and system architectures, including x86 and ARM.
• Experience with on-chip interconnects and industry-standard interfaces such as AXI and PIPE.

Academic Credentials

• Masters or bachelor in electrical or computer engineering

Benefits offered are described: AMD benefits at a glance.

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.

This posting is for an existing vacancy.