Hybrid PCIe Verification Engineer (UVM/SystemVerilog)

Advanced Micro Devices; Markham; Hybrid; CAD 90,000 - 130,000; Full time

Job summary

AMD is seeking a Verification Engineer to join the PCIe Subsystem team. You will develop and refine SystemVerilog/UVM testbenches, work with architects and RTL designers, and drive verification plans for new PCIe features.

The role demands strong communication and problem-solving to ensure robust RTL designs. Ideal candidates have hands-on experience with PCIe, SATA, Ethernet, and a track record in complex verification environments, with a focus on memory sub-systems and performance goals.

Qualifications

• Experience in modern processor architecture and digital design verification.
• Hands-on Verilog/SystemVerilog/UVM testbench development for PCIe features.
• Ability to collaborate across sites/time zones and communicate clearly.

Responsibilities

• Develop and enhance SystemVerilog/UVM-based testbenches for PCIe features.
• Collaborate with architects and RTL designers to build robust memory sub-system verification.
• Create staging and test plans for new feature development and validation tasks.
• Test a design to meet functional and performance goals and own verification tasks.
• Automate validation workflows and improve productivity with AI tools.

Skills

SystemVerilog

UVM

Testbenches

PCIe

Verifications

Communication

Education

Bachelor’s or Master’s degree

Tools

VCS

Debussy

Verdi

Job description

AMD is seeking a Verification Engineer to join the PCIe Subsystem team. You will develop and refine SystemVerilog/UVM testbenches, work with architects and RTL designers, and drive verification plans for new PCIe features.

The role demands strong communication and problem-solving to ensure robust RTL designs. Ideal candidates have hands-on experience with PCIe, SATA, Ethernet, and a track record in complex verification environments, with a focus on memory sub-systems and performance goals.