Remote Graphic design Expert - Data Labelling

Workada; Vancouver; Hybrid; CAD 90,000 - 130,000; Part time

Job summary

NeurealM/ Microchip in Vancouver, BC, is seeking a Design Verification Engineer for a contract role. The candidate will develop verification environments and execute testbenches for ASIC/SoC designs, ensuring high-quality digital designs.

You will create functional, regression, and constrained-random tests, analyze coverage, debug RTL and simulation issues, and verify interfaces like PCIe and AMBA/AXI. Scripting skills in Python/Perl/Shell are required.

Qualifications

• Bachelor's or Master's in Electrical, Electronics or Computer Engineering.
• Strong SystemVerilog and UVM experience required.
• Experience with ASIC/SoC verification and RTL debugging required.

Responsibilities

• Develop verification environments and testbenches using SystemVerilog and UVM.
• Create and execute functional, regression, and constrained-random tests.
• Analyze functional/code coverage and drive coverage closure.
• Debug RTL and simulation failures with design teams to resolve issues.
• Verify protocols (AMBA/AXI, PCIe, Ethernet or similar).
• Automate testing and regression using Python, Perl or Shell scripting.

Skills

SystemVerilog

UVM

RTL

Digital design

Scripting

Education

Bachelor's/Master's in Electrical/Electronics/CE

Tools

VCS

Xcelium

Questa

Job description

Job Title: Design Verification Engineer

Client: NeurealM/ Microchip

Location: Vancouver, BC, Canada - Initial 1 month Hybrid then after Remote

Job Type: Contract

Job Summary

We are looking for a Design Verification Engineer with strong experience in ASIC/SoC verification to develop and execute verification environments and ensure high-quality digital designs.

Responsibilities

• Develop verification environments and testbenches using SystemVerilog and UVM.
• Create and execute functional, regression, and constrained-random tests.
• Analyze functional/code coverage and drive coverage closure.
• Debug RTL and simulation failures and work with design teams to resolve issues.
• Verify protocols such as AMBA/AXI, PCIe, Ethernet, or similar interfaces.
• Automate testing and regression using Python, Perl, or Shell scripting.

Required Skills

• Strong SystemVerilog & UVM experience.
• Solid understanding of RTL, digital design, and ASIC/SoC verification.
• Experience with simulation tools such as VCS, Xcelium, or Questa.
• Strong debugging and scripting skills.
• Bachelor's/Master's degree in Electrical, Electronics, or Computer Engineering.