ASIC Synthesis and STA Engineer - New Grad

Ciena Corporation; Ottawa; On-site; CAD 71,000 - 113,000; Full time

Benefits offered by this job

Medical plan

Dental plan

Vision plan

ESPP

EAP

Paid holidays

Paid sick leave

Vacation time

Paid family leave

Job summary

Ciena Corporation is seeking a Frontend ASIC Engineer in Ottawa to drive frontend implementation for IP subsystems, including synthesis, timing analysis, and clock-domain validation. You will verify RTL-to-gatelevel consistency and collaborate with ASIC integration, IP, and backend teams to align frontend and backend activities.

You will develop timing constraints, write automation scripts, and handle ECOs while contributing to deep submicron ASIC projects and deepsubmicron timing closure

Qualifications

• Must have knowledge of ASIC implementation flows (synthesis, timing analysis, LEC, CDC).
• Experience with RTL design principles and HDL languages is required.
• Ability to work effectively within multidisciplinary teams and meet project schedules.

Responsibilities

• Execute frontend implementation for IP subsystems, including synthesis and timing analysis.
• Develop timing constraints for subsystem integration and signoff.
• Verify RTL-to-gatelevel consistency through pre/post-layout stages and clock-domain checks.
• Collaborate with ASIC integration, IP, and backend teams to align frontend/backend activities.
• Create scripts and tools to optimize synthesis and timing workflows and handle ECOs.

Skills

ASIC implementation flows

RTL design principles

HDL languages

Cross-functional collaboration

Education

B.Sc. in Electrical Engineering or Computer Engineering

Tools

Synthesis tools

Static timing analysis tools

DFT (Design for Testability)

EDA tools familiarity

Job description

As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era.We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration.Through development opportunities, meaningful work, and flexibility,Ciena supports growth and well-being—on and off the job.Connect with a career that matters.The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions and are one of the main contributors to Ciena's success in the telecommunications industry.This role offers the opportunity to shape the front-end implementation of industry leading ASIC technology and contribute to the methodologies that keep Ciena at the forefront of high-performance optical networking.

How you will make an impact:

• Execute frontend implementation for assigned IP subsystems, including synthesis, static timing analysis, logical equivalence checking, and clock domain crossing validation
• Develop and maintain timing constraints to support synthesis and signoff for subsystem integration
• Perform logical equivalence verification between Register Transfer Level (RTL) and gatelevel netlists throughout pre and postlayout stages
• Validate clock domain crossings for toplevel ASIC integration to ensure functional integrity
• Create and optimize scripts, tools, and documentation that improve synthesis and static timing workflows
• Implement engineering change orders (ECOs) to support iterative design refinement
• Collaborate closely with ASIC integration, IP development, physical design, and external Electronic Design Automation (EDA) partners to align frontend and backend implementation activities

The must haves:

• B.Sc. in Electrical Engineering, Computer Engineering, or a related discipline (or equivalent experience)
• Knowledge of ASIC implementation flows, including synthesis, timing analysis, logical equivalence checking, and clock domain crossing validation
• Familiarity with RTL design principles and hardware description languages
• Ability to work effectively within multidisciplinary engineering teams and manage deliverables to project schedules

Nice to haves:

• Experience with additional frontend or backend design activities such as floorplanning, Design for Testability (DFT), or place and route
• Industry experience using synthesis and/or static timing analysis tools within an ASIC development environment
• Handson exposure to deepsubmicron ASIC technologies and advanced timing closure methodologies
• Scripting experience (e.g., Python, Tcl, or similar) to enhance automation and debug workflows
• Background supporting DSPcentric or highspeed ASIC development programs
• Experience working with external EDA vendors or foundry technology teams

Pay Range: The annual salary range for this position is $70,700 - $112,900 Pay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available. Non-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence. At Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination. Ciena is an Equal Opportunity Employer, including disability and protected veteran status. If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

Benefits:

• medical, dental, and vision plans
• participation in 401(K) (USA) & DCPP (Canada) with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company-paid holidays
• paid sick leave
• vacation time
• Paid Family Leave and other leaves of absence

Dig deeper into who we are, what we do, and what you can expect as a member of our team. Meet the people who are shaping the future of communication and explore the culture we’ve built together at CienaLife.