Intern, DSP/AI Processor HW Design & Verification

Qualcomm; Markham; On-site; CAD 55,000 - 103,000; Full time

Benefits offered by this job

Housing stipend

Job summary

Qualcomm Canada ULC is seeking ASIC design and verification engineering interns to contribute to design, verification, and modelling of HW IP blocks for ML applications. Under supervision, you will gain hands-on experience across SystemVerilog, SystemC, and Python, learning multiple phases from specification to post-silicon debug.

Candidates must be enrolled in a bachelor’s or master’s program in CS/EE and available for a 16‑month internship (May 2027 – Aug 2028). Housing stipend provided.

Qualifications

• Currently enrolled in a bachelor’s or master’s degree program in computer engineering, computer science, electrical engineering, or a related field.
• Must be available for 16 months: May2027 – August2028
• Expected graduation date of November2028 or later.
• 1+ years of academic experience with programming languages such as C, C++, Python, etc

Responsibilities

• Implement modules in hardware design languages such as SystemVerilog and HLS C/C++/ SystemC
• Implement tests at both module and sub‑system levels using UVM and SystemVerilog
• Identify interface requirements for modules developed by others and integrate them into larger subsystems
• Implement reference and bus‑functional models using C++, SystemC, or Python
• Implement design/verification methodology and automation using Python, Perl, or TCL
• Implement and debug constraints to achieve netlist synthesis and static timing closure
• Make significant contributions to silicon debug and analysis
• Perform power analysis to identify/fix power bugs and contribute to power modelling/reporting
• Step into many phases of ASIC development from specification -> microarchitecture -> RTL coding -> verification -> synthesis -> optimization -> physical design -> post‑silicon debug/correlation

Skills

Digital Logic

Verilog/VHDL

Teamwork

Communication

Education

BS or MS in Computer Engineering, CS or EE

Tools

SystemVerilog

SystemC

HLS C/C++

Python

Job description

Qualcomm Canada ULC is seeking ASIC design and verification engineering interns to contribute to design, verification, and modelling of HW IP blocks for ML applications. Under supervision, you will gain hands-on experience across SystemVerilog, SystemC, and Python, learning multiple phases from specification to post-silicon debug.

Candidates must be enrolled in a bachelor’s or master’s program in CS/EE and available for a 16‑month internship (May 2027 – Aug 2028). Housing stipend provided.