Senior Fpga Developer

Caderno Nacional; Rio de Janeiro; Presencial; BRL 250 000 - 400 000; Tempo integral

Resumo da oferta

A Caderno Nacional busca Engenheiro FPGA sênior para assumir a arquitetura de FPGA de nossos produtos de teste e medição de comunicações. O profissional atuará como autoridade técnica, definindo caminhos de design, IPs, floorplanning e estratégias de timing para designs multi-Gbps, com foco em entregar soluções robustas.

Você será mentor de a equipe, resolverá problemas complexos de bring-up de silicon e board, e terá influência direta nos ciclos de desenvolvimento do HW/FW, interagindo com

Qualificações

• BSc ou MSc em Engenharia Elétrica/Computação com 12–15 anos de experiência.
• At least 5+ anos arquitetando e fechando timing em designs FPGA multi-Gbps com SerDes/transceptor.
• Experiência comprovada com Verilog/SystemVerilog/VHDL no desenvolvimento de FPGA de alta velocidade.
• Experiência em Ethernet de alta velocidade (10M a 1.6T) e pilhas IP.

Responsabilidades

• Definir e conduzir arquitetura FPGA de ponta a ponta, incluindo trade-offs de IP, floorplanning e timing closure para designs multi-Gbps.
• Atuar como ponto final de escalonamento técnico para problemas de FPGA e orientar engenheiros, liderando debug de silicon e boot de board.

Conhecimentos

Verilog/SystemVerilog/VHDL

FPGA transceivers

Timing closure

UVM verification

Git

Comunicação

Mentoria

Ethernet de alta velocidade

Formação académica

Engenharia Elétrica/Computação

Ferramentas

Ferramentas de FPGA (AMD/Altera)

Toolchains e floorplanning

Descrição da oferta de emprego

Segmento: Não Informado

Atividades

A leader in light management technologies for 3D sensing, anti-counterfeiting, consumer electronics, industrial, automotive, government and aerospace applications. Employees working on this project are passionate about supporting customer success and we welcome people who bring their best every day to the company – to question, to collaborate and to push for solutions that will delight our customers.

About the Role

We are seeking a Principal/Staff-level FPGA Engineer — a recognized technical authority — to own FPGA architecture for our state-of-the-art Communications Test & Measurement products.

Responsibilities

• The successful candidate will define and drive end-to-end FPGA architecture, including make/buy tradeoffs on IP, floorplanning and timing closure strategy for multi-gigabit designs, and DFX approach, using Verilog/SystemVerilog/VHDL and industry-leading simulation, synthesis, place-and-route, and formal/UVM verification tools.
• This person will serve as the final technical escalation point for FPGA design and debug issues across the team, mentor other FPGA engineers, and lead root-cause debug of silicon and board bring-up issues that could not be resolved elsewhere.

Qualifications

• BS or MS degree in Electrical and/or Computer Engineering with a minimum of 12-15 years of relevant experience, including at least 5+ years specifically architecting and closing timing on multi-Gbps SerDes/transceiver-based FPGA designs.

Required Skills

• Demonstrated expertise architecting and implementing high-speed FPGA designs using Verilog/SystemVerilog and/or VHDL required.
• Deep, hands-on expertise with FPGA transceivers, hard IP, and PLLs — including timing closure, equalization, and link debug at multi-Gbps rates — required (not incidental exposure).
• Demonstrated experience closing timing and debugging link-layer issues on high-speed Ethernet (10M to 1.
  6T) and IP protocol stacks in production designs.
• Proven expertise with optical interfaces and modules (SFPs, QSFPs) in shipped products.
• Deep working knowledge of VLANs, MPLS, VPLS, and Voice/Video over IP (VoIP, IPTV).
• Extensive experience with AMD or Altera FPGA devices and their full implementation toolchains, including advanced timing closure and floorplanning techniques.
• Proven experience with formal verification and/or UVM-based verification methodologies, not limited to directed testbenches.
• Demonstrated track record of taking FPGA designs from architecture through volume production, including systems-level tradeoffs across the HW/FW boundary.
• Version control experience using Git or similar tools.
• Exceptional written and oral communication skills, including the ability to mentor engineers and communicate architecture decisions with stakeholders across the world.
• Exceptional analytical and organizational skills, with an uncompromising commitment to accuracy and technical rigor in a fast-paced product environment.

Preferred Skills

Languages: English: B2 Upper Intermediate

Dias da Semana

Não Informado

Horário / Período

Não Informado

Os interessados devem se candidatar através do portal Caderno Nacional