Intern: Application Engineering - Formal Verification

Cadence; Belo Horizonte; Presencial; BRL 12 000 - 20 000; Tempo parcial

Vantagens oferecidas por esta oferta de emprego

Competitive benefits

Resumo da oferta

Cadence in Belo Horizonte, Brazil is looking for a motivated Intern for Application Engineering focused on Formal Verification methodologies. You’ll receive training to become an expert in industry-leading technologies.

Your role will include providing technical support to customers, conducting root cause analyses, and working closely with R&D on verification issues. Ideal candidates are those pursuing a Bachelor’s in relevant fields.

Qualificações

• Ongoing Bachelor in Electrical Engineering, Control and Automation Engineering, or related areas.
• Graduating in mid-2027.
• Excellent verbal and written communication skills in Portuguese and English.

Responsabilidades

• Activities focused on Formal Verification field, mentored by experienced colleagues.
• Provide technical support to customers in RTL verification solutions.
• Conduct root cause analysis and provide resolution to customer technical issues.
• Run customer test cases, create workarounds, test and deliver R&D fixes.
• Close collaboration with R&D on issues using established protocols.

Conhecimentos

Excellent verbal and written communication skills in Portuguese and English

Good problem-solving skills

Strong interpersonal and communication skills

A strong interest in learning technical topics

Formação académica

Ongoing Bachelor in Electrical Engineering or related fields

Ferramentas

Scripting languages (TCL, Python)

RTL (Verilog or VHDL)

Descrição da oferta de emprego

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems Inc. is looking for a motivated Intern: Application Engineering - Formal Verification to work with us in Belo Horizonte, Brazil.

As an Application Engineer Intern, you will be trained to become an expert in Formal Verification methodologies in the System Verification Group – Technical Field Operations (TFO-SVG) in Belo Horizonte. The TFO-SVG group works with Xcelium, Palladium, Protium, Jasper, VIPs, and other Cadence Digital Functional Verification tools. The application engineers provide technical support, enabling customers to effectively deploy our industry‑leading technology, focused on RTL‑level verification products. You will be trained in a Digital Verification & Simulation focused team working with our Jasper Formal Verification Platform, complimentary tools, and its customers to understand their needs and provide guidance on the best technologies and methodologies to enable their success, coming up with innovative solutions to address the industry’s most challenging problems. You’ll be mentored by experienced professionals to learn languages, tools, and verification methodologies from scratch.

Working at Cadence is very dynamic, fast‑paced, and integrated with other teams all around the world.

Job Description

• Activities focused on the Formal Verification field as mentioned above, mentored by experienced colleague, and reporting to higher management.
• Provide technical support to customers and field personnel in RTL verification solutions focused on the Jasper tool.
• Conduct root cause analysis and provide resolution to customer technical issues.
• Run customer test cases to verify problems, create workarounds when possible, test and deliver R&D fixes.
• Close collaboration with R&D on issues using established protocols.
• Author application notes and help provide feedback on documentation.
• Use scripting languages like TCL for flow development, automation and enhancing design methodologies.

Requirements

• Ongoing Bachelor in Electrical Engineering, Control and Automation Engineering, Systems Engineering, Electronics Engineering, Computer Science, Information Systems, Computational Mathematics, or related areas.
• Graduating in mid‑2027.
• Excellent verbal and written communication skills in Portuguese and English.
• Good problem‑solving skills.
• Strong interpersonal and communication skills.
• A strong interest in learning the technical topics mentioned above.

Nice To Have

• Experience in scripting languages such as TCL and Python is a plus.
• Exposure to RTL (Verilog or VHDL) is a plus.

Additional Job Details

• Employment category: Internship.
• Employment term: 20 hours/week.
• Competitive benefits.
• Av. do Contorno 5800, Savassi, Belo Horizonte, Minas Gerais.