Senior Hardware Design Engineer West Coast, United States

AccelerComm Ltd; Costa Rica; Híbrido; BRL 614 125 - 818 833; Tempo integral

Resumo da oferta

AccelerComm Ltd is seeking Senior Hardware Design Engineers to work on space-qualified devices for a satellite-based 5G base station project. The role focuses on RTL design, validation on FPGA platforms, and close collaboration with algorithm/system teams to deliver high-efficiency, reliable hardware.

You will contribute to the end-to-end design flow, from micro-architecture to verification and physical implementation, applying industry-standard methods and tooling.

Qualificações

• Experience with RTL languages for complex ASIC/FPGA products.
• Strong ability to optimize timing and hardware resources for high-throughput DSP tasks.
• Experience with EDA tools for simulation and synthesis.

Responsabilidades

• Translate requirements into RTL micro-architectures for RTL implementations.
• Implement designs for FPGA and ASIC using standard techniques and testbenches.
• Deploy designs onto FPGA platforms for validation and system integration.
• Adhere to AccelerComm engineering practices and seek efficiency improvements.
• Collaborate across the full design flow: architecture, verification, and physical implementation.

Conhecimentos

Verilog

SystemVerilog

ASIC/FPGA design

Timing optimization

Power management

EDA tools

Cross-team collaboration

Ferramentas

C++/SystemC

PCIe

JESD

AMBA

Python

Descrição da oferta de emprego

Senior Hardware Design Engineer

Department: US Jobs

Employment Type: Permanent

Location: West Coast, United States

Description

We are looking for multiple Senior Design Engineers who will work on revolutionary technology that is at the leading edge of non-terrestrial communications, a 5G base station to be deployed on board satellites. This technology will underpin the next generation of mobile standards, giving complete coverage to the entire globe. AccelerComm develops the baseband signal processing technology, using hardware acceleration to generate world-leading error resilience, capacity and power efficiency.

You will work on the latest generation space-qualified devices, delivering standalone IP and integrated IP solutions.

Key Responsibilities

As a Senior Hardware Design Engineer, you will:

• Work closely with the Algorithm and System Architecture teams to understand requirements and translate them into mirco-architectures for RTL implementations
• Implement designs targeting both FPGA and ASIC using industry standard techniques, including the creation of appropriate testbenches
• Deploy your designs onto the latest FPGA development platforms for validation and system integration
• Actively engage with and adhere to AccelerComm engineering methodology, processes and design techniques, being able to offer improvements to efficiency and quality for both the design flow and the final product
• Collaborate with colleagues across the whole design flow: micro-architecture, design, verification, physical implementation and optimisation for ASIC and FPGA

Skills, Knowledge and Expertise

Essential:

• Expert knowledge of an RTL language (Verilog, SystemVerilog) for complex ASIC/FPGA products
• A strong skillset in delivering digital designs in the ASIC and FPGA industry
• Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis
• Track record in collaborating across teams to produce integrated solutions
• Experience in technical documentation writing – design specifications, user guides, verification plans
• Expert user of EDA tools for simulation and synthesis

Desirable:

• Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming)
• Familiarity with the AMBA bus protocols
• Understanding of UVM verification techniques or practical experience using UVM for IP verification
• Experience using C++/SystemC for design modelling and integration
• Experience with high speed interfaces such as PCI-E or JESD
• Knowledge of a scripting language, such as Python
• Knowledge and appreciation of project methodologies across the design lifecycle, including agile and waterfall, requirement capture and traceability
• Experience with AMD FPGAs and the associated design tools or with any EDA’s ASIC backend tools