Wanted: Senior Fpga Developer

Luxoft; Dourados; Presencial; BRL 300 000 - 520 000; Tempo integral

Resumo da oferta

A Luxoft está buscando um engenheiro FPGA sênior para liderar a arquitetura de FPGA de nossos produtos de teste e medição de comunicações. O papel envolve decisões de IP, floorplanning e timing closure para designs multi-gigabit.

Você atuará como ponto de escalonamento técnico, mentorando a equipe e conduzindo o debug de silicon e bring-up de placa, com foco em desempenho e fiabilidade.

Qualificações

• Formação em Engenharia Elétrica ou de Computação com pelo menos 12–15 anos de experiência relevante, com 5+ anos em arquitetar e fechar timing em designs FPGA multi-Gbps.
• Experiência prática com transceivers, IPs duros e PLLs, com timing closure, equalização e debug de link em velocidades multi-Gbps.
• Histórico de fechar timing e debugar problemas de link-layer em Ethernet de alta velocidade e pilhas IP em designs de produção.

Responsabilidades

• Definir e conduzir arquitetura FPGA ponta a ponta, incluindo trade-offs de IP, floorplanning e timing closure em designs multi-gigabit.
• Atuar como ponto final de escalonamento técnico para desenho FPGA, orientar engenheiros e liderar debug de silicon e bring-up de boards.

Conhecimentos

Verilog/SystemVerilog

VHDL

FPGA timing closure

SerDes/transceivers

10M to 1.6T Ethernet

UVM verification

Git

Comunicação

Mentoria

Formação académica

Bacharel/Mestre em Engenharia Elétrica ou de Computação

Ferramentas

Altera

Xilinx

Ferramentas de implementação/clocking

Descrição da oferta de emprego

Wanted: Senior FPGA Developer Luxoft dourados, estado de mato grosso do sul, br

Descrição da vaga

About the Company

Working for a global provider of network test, monitoring and assurance solutions for telecommunications, cloud, enterprises, first responders, military, aerospace, and railway. A leader in light management technologies for 3D sensing, anti-counterfeiting, consumer electronics, industrial, automotive, government and aerospace applications. Employees working on this project are passionate about supporting customer success and we welcome people who bring their best every day to the company – to question, to collaborate and to push for solutions that will delight our customers.

About the Role

We are seeking a Principal/Staff-level FPGA Engineer — a recognized technical authority — to own FPGA architecture for our state-of-the-art Communications Test & Measurement products.

Responsibilities

• The successful candidate will define and drive end-to-end FPGA architecture, including make/buy tradeoffs on IP, floorplanning and timing closure strategy for multi-gigabit designs, and DFX approach, using Verilog/SystemVerilog/VHDL and industry-leading simulation, synthesis, place-and-route, and formal/UVM verification tools.
• This person will serve as the final technical escalation point for FPGA design and debug issues across the team, mentor other FPGA engineers, and lead root-cause debug of silicon and board bring-up issues that could not be resolved elsewhere.

Qualifications

• BS or MS degree in Electrical and/or Computer Engineering with a minimum of 12-15 years of relevant experience, including at least 5+ years specifically architecting and closing timing on multi-Gbps SerDes/transceiver-based FPGA designs.

Required Skills

• Demonstrated expertise architecting and implementing high-speed FPGA designs using Verilog/SystemVerilog and/or VHDL required.
• Deep, hands-on expertise with FPGA transceivers, hard IP, and PLLs — including timing closure, equalization, and link debug at multi-Gbps rates — required (not incidental exposure).
• Demonstrated experience closing timing and debugging link-layer issues on high-speed Ethernet (10M to 1.6T) and IP protocol stacks in production designs.
• Proven expertise with optical interfaces and modules (SFPs, QSFPs) in shipped products.
• Deep working knowledge of VLANs, MPLS, VPLS, and Voice/Video over IP (VoIP, IPTV).
• Extensive experience with AMD or Altera FPGA devices and their full implementation toolchains, including advanced timing closure and floorplanning techniques.
• Proven experience with formal verification and/or UVM-based verification methodologies, not limited to directed testbenches.
• Demonstrated track record of taking FPGA designs from architecture through volume production, including systems-level tradeoffs across the HW/FW boundary.
• Version control experience using Git or similar tools.
• Exceptional written and oral communication skills, including the ability to mentor engineers and communicate architecture decisions with stakeholders across the world.
• Exceptional analytical and organizational skills, with an uncompromising commitment to accuracy and technical rigor in a fast-paced product environment.

Preferred Skills

Languages: English: B2 Upper Intermediate

Criar um alerta de emprego para esta pesquisa

Wanted: Senior FPGA Developer dourados, estado de mato grosso do sul, br