PRINCIPAL ENGINEER/MTS, FECOS CPIE DEVICE

MICRON SEMICONDUCTOR ASIA OPERATIONS PTE LTD; Região Norte; Presencial; BRL 180 000 - 240 000; Tempo integral

Resumo da oferta

MICRON SEMICONDUCTOR ASIA OPERATIONS PTE LTD is seeking a senior engineer to enable technology ramp in high-volume CMOS and memory production. You will work on performance improvement, design and test optimisation, and process simplification while collaborating across functions to solve device and yield challenges.

The role requires strong semiconductor physics knowledge, 5+ years of relevant experience, and flexibility for occasional travel. Proficiency in data analysis and Python is a plus.

Qualificações

• 5+ years of relevant experience; a master's or PhD is preferred.
• Wafer fab process or process integration experience; FinFET/GAA preferred.
• Solid semiconductor physics knowledge and transistor basics.
• Understanding of wafer fabrication areas, tool sets and tuning knobs.
• Strong data analysis skills using JMP, Spotfire or similar tools.
• Good ownership and collaborative work approach.
• Open to learning new skills in a new environment.
• Proficient with MS Office; Python is a plus.
• Occasional international travel may be required.

Responsabilidades

• Enable technology ramp in high-volume production for CMOS and memory devices.
• Improve device performance with variability reduction and robustness focus.
• Support design and test optimisation to enhance manufacturability and performance.
• Identify and implement process simplification and working-method improvements.
• Lead or contribute to cross-functional problem-solving for device, yield and quality.

Conhecimentos

Data analysis

Python

MS Office

Formação académica

Master's or PhD in Physics or Engineering

Ferramentas

JMP

Spotfire

MS Office

Descrição da oferta de emprego

Job Responsibilities

• Enable technology ramp in high-volume production for CMOS and memory devices.

• Improve device performance with a focus on variability reduction and robustness.

• Support and execute design and test optimisation to enhance manufacturability and performance.

• Identify and implement process simplification and working methodology improvements.

• Lead or actively contribute to cross-functional problem-solving for device, yield, and quality issues.
  

Job Requirements

• Minimum 5 years of relevant working experience is required. A master's or Ph.D. degree in Physics or Engineering areas is preferred.

• Working experience in wafer fab process or process integration engineering. Direct experience in advanced CMOS device technology such as FinFET or GAA is preferable.

• Proven knowledge in semiconductor physics and understanding of transistor operations, scaling limitations and reliability, basic knowledge of CMOS circuits and characterisation methods.

• Understanding of wafer fabrication process areas, including tool sets, process mechanisms, tuning knobs, etc.

• Excellent data analysis skills using software (JMP, SPOTFIRE, etc).

• Strong task ownership, self-motivated to work with other team members to make progress collaboratively.

• Open-minded attitude to learn new skills and could adapt to a new working environment swiftly.

• Good digital literacy with MS Office. Programming capability such as Python is a plus.

• Occasional international business travel is required for this position.