Senior DRAM Periphery Circuit Architect (DTCO/Tapeout)

Imec

Heverlee

On-site

EUR 90,000 - 130,000

Full time

6 days ago

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Job summary

imec is seeking a Senior DTCO DRAM Periphery Circuit Designer/Architect to join its memory design and pathfinding activities. You will lead the design and exploration of advanced DRAM periphery circuits, ensuring robust, high-performance, and energy-efficient solutions through close interaction with subarray, bank, and macro-level architecture.

You will work on silicon proof-of-concepts to tapeout, bridging transistor-level circuit design, array organization, and macro architecture, with

Qualifications

Master's or PhD in Electrical Engineering or related field.
6+ years in DRAM industry focused on periphery circuit design.
Deep understanding of DRAM array organization and periphery interaction with protocol.
Hands-on experience designing DRAM peripheral circuits and related submodules.
Experience with silicon bring-up, tape-outs, hardware debug is a plus.
Proficiency with Virtuoso IC design, Hspice, and Calibre DRC/LVS.
Ability to work in multidisciplinary teams and communicate across domains.

Responsibilities

Lead design and exploration of advanced DRAM periphery circuits.
Bridge transistor-level design with array organization and macro architecture.
Design, analyze, and optimize row/column path circuitry, sense amps, write-path, precharge, timing logic.
Contribute to architectural decisions at subarray, bank, macro level.
Tape-out and demonstrator/test-chip activities.