Senior DTCO DRAM Periphery Circuit Designer / Architect

imec; Vlaams-Brabant; Sur place; EUR 90 000 - 120 000; Plein temps

Résumé du poste

Imec seeks a senior engineer to lead DRAM periphery design and analysis. You will drive circuit exploration that enables robust, high‑performance DRAM solutions, coordinating across transistor‑level design, array organization, and macro architecture.

You will contribute to silicon bring‑up, tapeouts and test‑chip activities, while collaborating with device, process, and DTCO teams to translate memory concepts into practical circuit implementations.

Qualifications

• Master's or PhD in Electrical Engineering, Electronics or related field.
• At least 6 years in DRAM industry focused on periphery circuit design.
• Deep understanding of DRAM array organization and interaction with periphery and protocol.
• Hands-on experience designing and analyzing DRAM peripheral circuits.

Responsabilités

• Design, analyze and optimize DRAM peripheral blocks such as row/column path circuitry and sense-amplifier related functions.
• Bridge transistor-level design to macro architecture and participate in tapeout readiness.
• Understand DRAM access flow and protocol timing implications across design stages.
• Collaborate with circuit designers, device experts and process integration teams.

Connaissances

DRAM design

Periphery circuit design

Layout-aware design

Cross-functional collaboration

Hardware debugging

Formation

Master's or PhD in Electrical Engineering or Electronics

Outils

Virtuoso IC design

Hspice

Calibre DRC/LVS

Description du poste

Join imec’s memory design and pathfinding activities and take a leading role in the design and exploration of advanced DRAM periphery circuits.

What you will do

In this position, you will join imec’s memory design and pathfinding activities and take a leading role in the design and exploration of advanced DRAM periphery circuits. You will work on the circuits that enable full DRAM operation, with a strong understanding of how they interact with the memory array, the array hierarchy, and the external DRAM protocol.

You will work on bringing silicon proof‑of‑concepts to tapeout, bridging transistor‑level circuit design, array organization, and macro‑level architecture, with the objective of enabling robust, high‑performance, and energy‑efficient DRAM solutions.

You will design, analyze, and optimize key DRAM peripheral building blocks such as row and column path circuitry, wordline‑related drivers, sense‑amplifier‑related functions, write‑path circuits, precharge and equalization functions, control and timing logic, data‑path and address‑path circuitry, and voltage‑generation or regulation blocks where relevant.

You will be expected to understand the complete DRAM access flow, including array activation, read, write, precharge, refresh‑related behavior, and the protocol timing implications of these operations. You will work in a layout‑aware manner, taking ownership from specification through circuit design, simulation, verification, and implementation readiness.

You will also contribute to architectural decisions at subarray, bank, and macro level by understanding the trade‑offs between performance, power, area, robustness, and technology assumptions, for emerging technologies. The role therefore requires not only strong block‑level design capability, but also the ability to reason across array organization and protocol‑level operation.

What we do for you

We offer a full‑time position in a highly innovative and multidisciplinary environment, with the opportunity to work on advanced memory technologies and future‑oriented DRAM solutions. This is a chance to work in a rapidly growing, multi‑disciplinary team with strong interaction across circuit design, devices, process integration, and system‑facing research.

This is an exciting role with significant technical ownership and visibility, where your work will directly contribute to memory roadmap definition, circuit innovation, and demonstrator or test‑chip activities. Internal imec job‑description material explicitly frames these roles around enabling future semiconductor memory technologies and interacting with major foundry, fabless, and EDA partners in imec’s ecosystem. You will have the opportunity to collaborate closely with circuit designers, device experts, process integration engineers, architects, and DTCO/STCO teams, while influencing how advanced memory concepts are translated into practical circuit and macro implementations.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth.

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.

Who you are

• You have a Master’s degree or PhD in Electrical Engineering, Electronics, or a related field.
• You bring strong industrial experience in DRAM design, with at least 6 years in the DRAM industry focused on periphery circuit design.
• You have deep understanding of DRAM array organization and the interaction between array, periphery, and protocol. This includes familiarity with array hierarchy, subarrays, banks, rows, columns, row‑buffer behavior, and the main operational sequences associated with DRAM access.
• You have hands‑on experience designing and analyzing DRAM peripheral circuits and understand the role of the main DRAM submodules, including row and column path circuitry, sensing‑related functions, data‑path and address‑path circuitry, control and timing logic, and supporting circuits such as voltage‑generation or regulation blocks where applicable.
• Experience with silicon bring‑up, tape‑outs, hardware debug, or product‑oriented DRAM development is a strong plus.
• You are fully acquainted with industry‑standard circuit‑design and verification tools, ideally including Virtuoso IC design, Hspice, and Calibre DRC/LVS.
• You have worked in multidisciplinary teams and can communicate effectively with experts spanning circuit design, architecture, modeling, technology, physical implementation, and hardware validation.

What would be a plus:

• You are comfortable translating architecture‑and‑protocol‑level requirements into transistor‑level circuit solutions, while keeping in mind layout, parasitics, robustness, and implementation feasibility.
• Exposure to high‑performance or high‑voltage DRAM periphery topics such as sense‑amplifier optimization, row‑decoder design, timing‑critical control paths, or voltage‑generation circuitry is highly valuable.

For imec UK: this position is open only to candidates who already hold a valid UK residence permit or work authorization. We are currently not able to provide UK visa sponsorship.