Senior Digital Design Engineer — SoC Power & IP Innovation

Cyient Limited; Belgique; On-site; EUR 55,000 - 75,000; Full time

Job summary

Cyient Limited in Belgium is seeking a Digital Design engineer to transform imaginative ideas into high-performance RTL/SoC IPs for RF CMOS and high-speed data communication. You will define micro-architecture, develop RTL using SystemVerilog/Verilog/VHDL, and drive low-power design.

Collaboration with verification and backend teams is essential to meet timing and power goals, while strong communication skills support cross-functional work. Minimum qualifications include a B.S./M.S.

Qualifications

• Bachelor or Master in Electrical/Computer Engineering or Computer Science with ≥4 years in digital design.
• Strong communication and presentation skills.
• Autonomous problem solving with proactive mindset.
• Experience with RTL design and testbench development.

Responsibilities

• Define micro-architecture for efficient and power-optimized designs.
• RTL development using SystemVerilog, Verilog, or VHDL.
• Implement low-power design (UPF) techniques.
• Conduct linting, CDC/RDC checks and synthesis constraints.
• Identify, select and integrate IPs (soft and hard).
• Collaborate with verification to develop verification plans.
• Coordinate with backend to meet timing and power targets.

Skills

SystemVerilog

Verilog

VHDL

RTL design

Testbench development

Low-power design

Education

Electrical Engineering

Computer Engineering

Computer Science

Tools

SystemVerilog

VHDL/Verilog

Job description

Cyient Limited in Belgium is seeking a Digital Design engineer to transform imaginative ideas into high-performance RTL/SoC IPs for RF CMOS and high-speed data communication. You will define micro-architecture, develop RTL using SystemVerilog/Verilog/VHDL, and drive low-power design.

Collaboration with verification and backend teams is essential to meet timing and power goals, while strong communication skills support cross-functional work. Minimum qualifications include a B.S./M.S.