Senior FPGA Design Engineer - Hybrid (Liège)

EVS; Seraing; Hybrid; EUR 65,000 - 90,000; Full time

Benefits offered by this job

Hybrid work model

Professional development

Job summary

EVS in Liège, Belgium, is seeking an experienced FPGA Design Engineer (medior/senior) to join its Hardware Engineering team. The role focuses on high-performance FPGA platforms for live video production, with hybrid work up to two days per week.

You will translate requirements into RTL, develop in Verilog/SystemVerilog (VHDL welcome), and own the full design flow from RTL to on-target validation, collaborating with cross-functional hardware, software and QA teams.

Qualifications

• Master’s degree in Electrical Engineering, Electronics, Computer Engineering or related field.
• At least 5 years of FPGA design experience in high-speed/data-intensive systems.
• Proficiency in Verilog/SystemVerilog or VHDL with simulation, synthesis and timing closure.
• Experience with DDR memory interfaces, PCI Express, high-speed Ethernet, video processing or codecs.
• Experience with FPGA toolchains: Vivado or Quartus.
• Proficient in Python, Tcl or shell for scripting.
• Strong English communication; French desirable.
• Able to work autonomously in a multidisciplinary team.

Responsibilities

• Design, implement and verify high-performance FPGA functions.
• Translate requirements into FPGA architectures and RTL components.
• Develop in Verilog/SystemVerilog with VHDL welcome.
• Own RTL design flow: simulation through on-target validation.
• Integrate interfaces such as DDR memory, PCI Express, high-speed Ethernet, or video codecs.
• Contribute to design reviews, documentation and tool improvements.
• Collaborate with system architects, PCB designers, software and QA teams.
• Support system bring-up and production releases.
• Mentor less-experienced engineers as needed.

Skills

Verilog/SystemVerilog

VHDL

English (professional)

Problem solving

Education

Master’s degree in Electrical Engineering / Electronics / Computer Engineering or related field

Tools

Vivado

Quartus

Python

Tcl

Shell scripting

Job description

EVS in Liège, Belgium, is seeking an experienced FPGA Design Engineer (medior/senior) to join its Hardware Engineering team. The role focuses on high-performance FPGA platforms for live video production, with hybrid work up to two days per week.

You will translate requirements into RTL, develop in Verilog/SystemVerilog (VHDL welcome), and own the full design flow from RTL to on-target validation, collaborating with cross-functional hardware, software and QA teams.