Design and Implementation of a Test Protocol Description Language for IEEE Std 1838 Flexible Parallel Ports

Imec; Vlaams-Brabant; Hybrid; EUR 8,900 - 13,000; Full time

Benefits offered by this job

Allowance provided

Job summary

imec is seeking a student in Computer Science, Informatics, or Electrical Engineering for a Master internship (9–12 months) in Belgium. The project focuses on designing and implementing a new test protocol description language to support diverse test-access mechanisms for embedded cores and chiplets, enabling compatibility with FPP interfaces.

The selected candidate should have strong programming skills (C++ or Python), knowledge of Verilog or VHDL, and be proficient in English in an

Qualifications

• Proficiency in at least one programming language (C++ or Python).
• Familiarity with hardware description languages (Verilog or VHDL).
• Interest in design-for-test (DfT) for digital ICs desirable.

Responsibilities

• Assist design and implementation of a test protocol language for chiplets and SoC test integration.
• Support development work for FPP and other test-access mechanisms.
• Contribute to documentation and testing activities for the language description toolchain.

Skills

C++

Python

Verilog

VHDL

Education

Computer Science

Electrical Engineering

Job description

/ Design and Implementation of a Test Protocol Description Language for IEEE Std 1838 Flexible Parallel Ports

Design and Implementation of a Test Protocol Description Language for IEEE Std 1838 Flexible Parallel Ports

Bridging the 3D-IC Test Gap: Standardized test protocols for IEEE Std 1838

This paradigm shift centers on decomposing a system-on-a-chip (SoC) into dedicated functional blocks, commonly referred to as chiplets. A chiplet is a small die with a well-defined function designed to be integrated alongside other chiplets within a single package as a multi-die stack. Common examples include computational processor cores, graphics units, AI accelerators, and specialized I/O controllers. Chiplets can be placed side-by-side on a large base die (an interposer), stacked vertically in a single tower, or combined in a hybrid configuration incorporating both architectures—referred to as 2.5D, 3D, and 5.5D integration, respectively. These modular approaches allow manufacturers to optimize costs by combining advanced process nodes with mature ones where appropriate. Furthermore, high-density vertical inter-die connections provide high bandwidth and low latency across stacked dies. These inter-die interconnects utilize micro-bumps or direct hybrid bonding pairs to establish physical and electrical bonds. Depending on the stack architecture, the interconnect may also incorporate through-silicon vias (TSVs) when bonding to the backside of a die, as well as interposer routing wires in 2.5D integration.

To improve test interoperability across multi-vendor dies, IEEE Std 1838 standardized the chiplet test-access wrapper. However, a formal description language for test-pattern retargeting remains an open need. IEEE Std 1687 and its subsequent amendments addressed modalized scan chain configurations using the Core Test Language (CTL) to describe test ports, test-access structures, and operating modes at the core level, alongside the Procedural Description Language (PDL) to specify test sequences, stimulus application, and access procedures for on-chip instruments or target chiplets. Nevertheless, IEEE Std 1687 primarily focuses on serial scan mechanisms rather than fully supporting IEEE Std 1838’s Flexible Parallel Port (FPP). Because the FPP is optional in IEEE Std 1838, parallel scan capabilities have lagged, even as increasing package complexity drives strong demand for high-throughput parallel scan test access. Furthermore, commercial EDA implementations of FPP interfaces remain inconsistent. Although Erik Jan Marinissen et al. proposed an FPP architecture description language based on Google Protocol Buffers at ETS’18 [1], it was not adopted by the IEEE 1838 working group, which prioritized defining a fixed test-access mechanism (TAM) for 3D-ICs.

To resolve these limitations, this project aims to design and implement a new description language that supports diverse test-access mechanisms for embedded cores and chiplets, while providing a unified description to enable the compatibility of the FPP interfaces. By decoupling test protocols from test patterns—a principle central to Macro Test [2]—software automation tools can perform core-to-chiplet test expansion, chiplet-to-package test translation, test scheduling, and pattern assembly directly on test protocols. This new description of test protocol expansion (e.g., from a chiplet boundary to the package pins) should support not only the FPP but also serial access mechanisms.

We are seeking a student in Computer Science, Informatics, or Electrical Engineering with excellent academic performance and a keen interest in learning about design-for-test (DfT) for digital integrated circuits (ICs). While deep knowledge of semiconductors is not a prerequisite, proficiency in at least one programming language (C++ or Python), one hardware description language (Verilog or VHDL), and English is essential, as imec is an international organization where English is the primary working language.

References:

[1] Yu Li, Ming Shao, Hailong Jiao, Adam Cron, Sandeep Bhatia, and Erik Jan Marinissen, “IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers”, 2018 IEEE 23rd European Test Symposium (ETS), Bremen, Germany, 2018, pp. 1-6, DOI: 10.1109/ETS.2018.8400690.

[2] Erik Jan Marinissen, “The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs”, Journal of Electronic Testing: Theory and Applications (JETTA), Volume 18, No. 4/5 (August 2002), pp. 435-454, DOI: 10.1023/A:1016545607915.

Type of internship: Master internship

Duration: 9~12 months

Required educational background: Computer Science, Electrotechnics/Electrical Engineering

The reference code for this position is 2026-INT-284. Mention this reference code in your application.

Imec allowance will be provided.

This market continues to demand integrated circuits (ICs) with higher performance, greater energy efficiency, and lower cost. As conventional transistor scaling faces increasing technical and financial hurdles, the drive to deliver compelling new IC products that meet market expectations is transitioning to innovations in multi-die stack assembly and packaging techniques.
This paradigm shift centers on decomposing a system-on-a-chip (SoC) into dedicated functional blocks, commonly referred to as chiplets. A chiplet is a small die with a well-defined function designed to be integrated alongside other chiplets within a single package as a multi-die stack. Common examples include computational processor cores, graphics units, AI accelerators, and specialized I/O controllers. Chiplets can be placed side-by-side on a large base die (an interposer), stacked vertically in a single tower, or combined in a hybrid configuration incorporating both architectures—referred to as 2.5D, 3D, and 5.5D integration, respectively. These modular approaches allow manufacturers to optimize costs by combining advanced process nodes with mature ones where appropriate. Furthermore, high-density vertical inter-die connections provide high bandwidth and low latency across stacked dies. These inter-die interconnects utilize micro-bumps or direct hybrid bonding pairs to establish physical and electrical bonds. Depending on the stack architecture, the interconnect may also incorporate through-silicon vias (TSVs) when bonding to the backside of a die, as well as interposer routing wires in 2.5D integration.
Because chiplet architectures offer extensive flexibility, this design paradigm splits the IC ecosystem into two distinct roles: chiplet providers and chiplet users. This division operates both intra-company and inter-company; in the latter case, the protection of design intellectual property rights (IPR) becomes critical. Consequently, test development becomes a distributed effort between provider and user. The chiplet provider, possessing intimate knowledge of the die's internal implementation, inserts Design-for-Testability (DFT) structures and generates die-level tests. The chiplet user, understanding the target application and system-level environment, sets quality targets, verifies that the chiplet is accessible from external package pins, and creates tests for all packaged chiplets. However, in modern 3D DFT architectures, external stack I/Os connect directly only to the bottom of the base die. Test stimuli must therefore be transported through intermediate dies in the stack up to the target die-under-test (DUT); similarly, test responses must travel back down through the stack to the external package pins. Addressing this requires a standardized language to exchange test-related information between provider and user, a unified test-access infrastructure, and software automation capable of translating and scheduling die-level tests at the package level.
To improve test interoperability across multi-vendor dies, IEEE Std 1838 standardized the chiplet test-access wrapper. However, a formal description language for test-pattern retargeting remains an open need. IEEE Std 1687 and its subsequent amendments addressed modalized scan chain configurations using the Core Test Language (CTL) to describe test ports, test-access structures, and operating modes at the core level, alongside the Procedural Description Language (PDL) to specify test sequences, stimulus application, and access procedures for on-chip instruments or target chiplets. Nevertheless, IEEE Std 1687 primarily focuses on serial scan mechanisms rather than fully supporting IEEE Std 1838’s Flexible Parallel Port (FPP). Because the FPP is optional in IEEE Std 1838, parallel scan capabilities have lagged, even as increasing package complexity drives strong demand for high-throughput parallel scan test access. Furthermore, commercial EDA implementations of FPP interfaces remain inconsistent. Although Erik Jan Marinissen et al. proposed an FPP architecture description language based on Google Protocol Buffers at ETS’18 [1], it was not adopted by the IEEE 1838 working group, which prioritized defining a fixed test-access mechanism (TAM) for 3D-ICs.
To resolve these limitations, this project aims to design and implement a new description language that supports diverse test-access mechanisms for embedded cores and chiplets, while providing a unified description to enable the compatibility of the FPP interfaces. By decoupling test protocols from test patterns—a principle central to Macro Test [2]—software automation tools can perform core-to-chiplet test expansion, chiplet-to-package test translation, test scheduling, and pattern assembly directly on test protocols. This new description of test protocol expansion (e.g., from a chiplet boundary to the package pins) should support not only the FPP but also serial access mechanisms.
We are seeking a student in Computer Science, Informatics, or Electrical Engineering with excellent academic performance and a keen interest in learning about design-for-test (DfT) for digital integrated circuits (ICs). While deep knowledge of semiconductors is not a prerequisite, proficiency in at least one programming language (C++ or Python), one hardware description language (Verilog or VHDL), and English is essential, as imec is an international organization where English is the primary working language.
References:
[1] Yu Li, Ming Shao, Hailong Jiao, Adam Cron, Sandeep Bhatia, and Erik Jan Marinissen, “IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers”, 2018 IEEE 23rd European Test Symposium (ETS), Bremen, Germany, 2018, pp. 1-6, DOI: 10.1109/ETS.2018.8400690.
[2] Erik Jan Marinissen, “The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs”, Journal of Electronic Testing: Theory and Applications (JETTA), Volume 18, No. 4/5 (August 2002), pp. 435-454, DOI: 10.1023/A:1016545607915.

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