Senior DFT Engineer

Imec; Luik; On-site; EUR 90,000 - 120,000; Full time

Job summary

IMEC in Leuven, Belgium is seeking a Senior DFT Engineer to drive design-for-test strategies for complex SOCs in a world-leading R&D environment. You will architect DFT solutions and coordinate requirements with project teams to assure testability and performance.

You will implement innovative DFT techniques on SOCs and sub-systems, define timing for DFT test modes, and work with boundary scan, MBIST, OCC/OPCG, and IJTAG standards. Relocation support is provided for international applicants.

Qualifications

• Five or more years of experience in DFT insertion and ATPG for SOCs.
• Hands-on experience with boundary scan, compression, MBIST/repair, OPCG/OCC.
• Strong knowledge of IEEE 1149.x and IJTAG standards.
• Experience defining/maintaining DFT flows in complex designs.
• Proficiency with Verilog/VHDL for test logic and TCL scripting.

Responsibilities

• Architect DFT solutions for SOCs with multiple sub-blocks and complex IPs.
• Coordinate/negotiate DFT requirements with project teams and customers.
• Implement and validate innovative DFT techniques on SOCs and subsystems.
• Define timing constraints for DFT test-modes.
• Insert boundary scan, compression, MBIST/repair, OCC for large-scale designs.
• Generate test patterns and improve fault coverage; support post-silicon test patterns.
• Collaborate with the physical design team on timing violations and signal integrity.
• Collaborate with the test engineering team on silicon characterization and validation.

Skills

DFT insertion and ATPG

Verilog/VHDL basics

DFT owner of sub-systems

DFT integration with PHY blocks

SDC constraints for DFT

Boundary scan, MBIST/repair, OPCG/OCC

IEEE 1149.1/1149.6/1687 (IJTAG)

EDA tools: Tessent, Genus/Modus

Tessent SSN

Scripting: TCL

Tools

Tessent (Siemens)

Genus/Modus (Cadence)

Simulation tools

Job description

Senior DFT Engineer

What you will do

As a Senior DFT Engineer, you leverage your expertise in Design-for-Test to develop cutting‑edge integrated circuits within our world-leading R&D environment. Working at the forefront of semiconductor technology, you play a pivotal role in ensuring the testability, quality, and performance of complex chip designs.

• Architect DFT solutions for SOCs with multiple sub‑blocks/partitions and complex soft/hard IPs with complex DFT requirements.
• Coordinate/Negotiate DFT requirements with the project teams and the customers.
• Implement, and validate innovative DFT techniques on SOCs and sub‑systems.
• Define timing constraints for DFT test-modes.
• Insert boundary scan, compression, MBIST/R(epair), OCC for large‑scale low‑power designs in advanced nodes (5nm and beyond).
• Generate test patterns, debug/improve fault coverage, support debug of post‑silicon test patterns, diagnose memory and scan issues.
• Work closely with the physical design team in the context of timing violations, signal/power integrity issues, routing congestion, etc.
• Work closely with the test engineering team on silicon characterization and validation.

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, ‘our corporate university’, we actively invest in your development to further your technical and personal growth.

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.

Who you are

• 5+ years of experience with DFT insertion and ATPG.
• Basic fluency with Verilog/VHDL to write code for test logic when needed.
• Experience as a DFT owner of sub‑systems including the insertion and verification of all DFT structures.
• Experience with DFT integration of complex PHY blocks (such as PCIe, UCIe, LPDDR5, etc.).
• Hands‑on experience with defining SDC constraints for DFT, and inserting/verifying boundary scan, compression, MBIST/repair, OPCG/OCC, ATPG, fault coverage improvement, test debug, for large low‑power designs in advanced nodes (5nm and beyond).
• Expert knowledge in IEEE 1149.1, 1149.6, and 1687 (IJTAG) standards and associated file formats (ICL, PDL).
• Preferably previous experience with defining/maintaining DFT flows.
• Experienced in EDA tools such as Tessent (Siemens), Genus/Modus (Cadence), and simulation tools.
• Experience using Tessent SSN is a plus.
• Experience with the IEEE1838 standard and DFT for chiplets (2.5D/3D) is a plus.
• Experienced in scripting languages, especially TCL.

Your presence at our HQ in Leuven/Belgium is required for this position. Relocation support is provided for international applicants.

IMEC and its affiliates will not accept unsolicited resumes from any source other than directly from a candidate. IMEC will consider unsolicited referrals and/or resumes submitted by vendors such as search firms, staffing agencies, professional recruiters, fee‑based referral services and recruiting agencies (hereafter “Agency”) to have been referred by the Agency free of charge. IMEC will not pay a fee to any Agency that does not have a prior written agreement with IMEC, validated by its HR department, in place regarding a specific job opening and allowing to submit resumes.