IC Physical Verification Engineer — Calibre Signoff

HCL Technologies Limited; Redmond; Remoto; AUD 136.000 - 276.000; Tempo pieno

Vantaggi offerti da questo lavoro

Medical insurance

Dental insurance

Vision insurance

401(k) plan

Paid time off

Paid holidays

Descrizione del lavoro

HCLTech in Redmond, WA is seeking a highly talented Physical Verification Engineer to ensure IC layout correctness, foundry compliance, and manufacturability before tape-out. You will own DRC, LVS, ERC, DFM, antenna and density checks and drive issues to closure, collaborating with design, layout and foundry teams.

The role includes scripting for PV automation, runset customization, and support for final tape-out packages.

Competenze

• Strong hands-on experience with Physical Verification and layout signoff.
• Expertise in Calibre DRC, LVS, PERC, and DFM.
• Strong experience in DRC/LVS debugging and closure.
• Good understanding of IC layout design, physical verification methodologies, and semiconductor process rules.
• Experience with antenna, density, ERC, and DFM checks.
• Experience with runset customization and foundry rule deck interpretation.
• Hands-on experience supporting tape-out and signoff activities.
• Strong Linux/Unix and scripting skills, such as Tcl, Perl, Python, or Shell.
• Strong debugging and root-cause analysis capabilities.

Mansioni

• Perform DRC, LVS, and ERC verification and drive issues through final signoff.
• Execute physical verification using Siemens Calibre, including DRC, LVS, PERC, and DFM.
• Perform antenna and density checks and resolve violations.
• Own layout signoff management and ensure physical verification closure before tape-out.
• Debug complex DRC/LVS violations and perform root-cause analysis.
• Customize and maintain runsets/decks based on project and foundry requirements.
• Interpret foundry process technology rules and translate them into verification requirements.
• Perform DFM compliance checks to ensure layout manufacturability.
• Work closely with layout, physical design, and circuit design teams to resolve verification issues.
• Interact with foundry teams for rule interpretation and clarification.
• Support preparation and validation of the final tape-out package.
• Develop scripts and automation to improve physical verification and debug efficiency.

Conoscenze

Physical verification

Calibre DRC/LVS/PERC/DFM

Antenna checks

Density checks

Scripting (Python/Tcl/Perl/Shell)

Tape-out support

Linux/Unix

Runset customization

Foundry rule interpretation

Debugging/root-cause analysis

Strumenti

Calibre

Synopsys IC Validator (ICV)

Descrizione del lavoro

HCLTech in Redmond, WA is seeking a highly talented Physical Verification Engineer to ensure IC layout correctness, foundry compliance, and manufacturability before tape-out. You will own DRC, LVS, ERC, DFM, antenna and density checks and drive issues to closure, collaborating with design, layout and foundry teams.

The role includes scripting for PV automation, runset customization, and support for final tape-out packages.