FPGA Development Intern: Build Ultra-Low Latency Trading

Stfrancis; Sydney; Hybrid; AUD 40,000 - 60,000; Full time

Benefits offered by this job

Optiver-covered flights and 住宿

Job summary

Optiver is seeking an FPGA Developer Intern in Australia. You will work with seasoned FPGA engineers to accelerate latency-critical trading systems and learn through an intensive 10-week program. You will be paired with a mentor and contribute to multiple areas, including design, testing, and data communication improvements.

You will gain hands-on experience with VHDL/Verilog, SystemVerilog, and Python/C++, while receiving training on trading fundamentals and software development processes.

Qualifications

• Enrolled in Electrical or Computer Engineering, penultimate year.
• Knowledge of HDL languages (VHDL/Verilog) and some Python/C++ experience.
• Interest in FPGA development and low-latency systems.

Responsibilities

• Develop latency-critical applications for trading systems.
• Collaborate with senior FPGA developers in a fast-paced learning environment.
• Design high-performance FPGA-based solutions and test benches.
• Participate in a world-class training program and mentorship initiatives.

Skills

HDL languages (VHDL/Verilog)

Python

C++

FPGA development

Low-latency design

Education

Electrical/Computer Engineering degree

Penultimate year student

Tools

SystemVerilog

VHDL

Job description

Optiver is seeking an FPGA Developer Intern in Australia. You will work with seasoned FPGA engineers to accelerate latency-critical trading systems and learn through an intensive 10-week program. You will be paired with a mentor and contribute to multiple areas, including design, testing, and data communication improvements.

You will gain hands-on experience with VHDL/Verilog, SystemVerilog, and Python/C++, while receiving training on trading fundamentals and software development processes.