Staff Engineer Mixed Signal Layout (f/m/div.)

Infineon Technologies AG; Villach; On-site; EUR 90,000 - 130,000; Full time

Job summary

Infineon Technologies AG in Austria seeks a Staff Engineer Mixed Signal Layout to drive full-custom IC layout for high‑frequency RF blocks and fast SerDes. You will optimize layouts, run comprehensive physical verifications, and manage parasitics to ensure signal integrity at multi‑gigabit data rates.

We value +5 years in CMOS/FinFET, strong RF expertise, and leadership to mentor junior engineers. Expect close collaboration with RF design, global teams, and a competitive compensation package.

Qualifications

• Degree in Electrical Engineering (FH or equivalent).
• 5+ years in CMOS/FinFET technology and analog/RF layout.
• Experience with high‑speed interfaces such as PCIe/Ethernet/USB or SerDes.
• Proficient in Cadence Virtuoso and Calibre for layout verification.
• Strong communication and leadership to guide a layout team.

Responsibilities

• Full-custom IC layout from schematic to tape-out for RF blocks.
• Optimize layout to prevent noise coupling and improve isolation.
• Run and debug physical verification (DRC/LVS/ERC and antenna checks).
• Analyze parasitics to ensure signal and power integrity at high freq.
• Lead and mentor layout engineers within the team.

Skills

CMOS & FinFET layout

RF Layout

Analytical skills

Leadership

Project management

English fluency

Education

Bachelor's degree in Electrical Engineering (FH)

Tools

Cadence Virtuoso

Siemens Calibre

Job description

#WeAreIn for jobs that impact everyone's life. What if your ideas could change the way the world connects, powers up, or thinks? As a Staff Engineer Mixed Signal Layout (f/m/div.) on our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life. Are you in?

Your role

• Full Custom Layout: Execute full-custom IC and block-level layout from schematic to tape‑out for high‑frequency RF blocks and high-speed SerDes components
• Layout Optimization: Implement precise matching techniques and isolation strategies to prevent noise coupling in sensitive analog front‑ends.
• Physical Verification: Run and debug full‑chip physical verifications including DRC, LVS, ERC, and Antenna rule checks.
• Parasitic Management: Analyze and minimize parasitic resistance, capacitance, and inductance to ensure signal and power integrity at high frequencies.
• Top‑Level Integration: Floorplanning, pad‑ring assembly, and final chip integration considering ESD, latch‑up, and electro‑migration (EM) guidelines.
• Leader- & Mentorship: Technical Leadership during project execution and mentor junior layout engineers within the team.

Your profile

• Education: A university (of applied sciences) degree in Electrical Engineering or comparable
• Experience: +5 years of hands‑on experience in CMOS and FinFET semiconductor technologies.
• RF Expertise: Proven track record in analog/RF IC layout including high‑speed interfaces (e.g., PCIe, Ethernet, USB, or custom SerDes) operating at multi‑gigabit data rates.
• Tool Expertise: High proficiency with industry‑standard EDA tools (Cadence Virtuoso, Siemens Calibre, …)
• Problem‑Solving: Excellent analytical skills to independently debug complex layout and physical verification issues.
• Communication Skills: Excellent communication skills to bridge technical gaps across global, multi‑disciplinary engineering teams.
• Leadership & Teamwork: Strong leadership skills with the ability to guide, motivate, and coordinate small layout team during the project execution and to collaborate closely with RF Design Engineers.
• Languages: Fluent in English;

We offer competitive salaries and additional benefits based on your performance, experience, and qualification. The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group G (https://www.feei.at/aktuelles/mindestloehne-und-gehaelter-eei/). The monthly salary is paid 14 times p.a. We offer a higher compensation depending on your expertise and skills.

• We offer competitive salaries and additional benefits based on your performance, experience, and qualification.
• The monthly salary is paid 14 times p.a.
• The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group G (https://www.feei.at/aktuelles/mindestloehne-und-gehaelter-eei/).
• We offer a higher compensation depending on your expertise and skills.

#WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game‑changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in?

We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity. Our hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply.

Please let your recruiter know if you need any accommodations during the interview process.

Learn more about our various contact channels and about Diversity & Inclusion at Infineon.