Digital Designer / RTL Design Engineer

microTECH Global LTD; Schweiz; Hybrid; EUR 70,000 - 100,000; Full time

Job summary

microTECH Global LTD seeks an experienced Digital Designer / RTL Design Engineer for a remote role with occasional on-site visits across Europe. You will design and implement low-power, multi-clock-domain digital blocks, write block specifications, and participate in architecture refinement.

The role requires SystemVerilog and VHDL RTL expertise, knowledge of low-power techniques, and collaboration with verification. SDC, CTS, and toolchain familiarity are important.

Qualifications

• Experience in low-power digital design and multiple clock domains.
• Ability to drive issues to closure in a distributed team.
• Proficient in SystemVerilog and VHDL RTL coding and verification.
• Familiar with SDC, STA review, and block optimization.

Responsibilities

• Write block specifications in DOORs based on architecture requirements.
• Participate in microarchitecture definition and design reviews.
• Develop RTL in SystemVerilog/VHDL with focus on power and area.
• Synthesize blocks with Fusion Compiler and write SDCs.
• Collaborate with Verification for corner cases and coverage closure.
• Perform LINT, CDC analysis, and Formality LEC checks.

Skills

SystemVerilog

VHDL RTL

Low power design

Multi-clock-domain design

Communications in English

RTL design optimization

Trade-off thinking

Tools

Fusion Compiler

SDC

Jasper Gold

LINT

Formality

DOORs

GIT

SVN

Python

Job description

Digital Designer / RTL Design Engineer

Duration: November 2026 - September 2027

Location: Remote with ramp up and some onsite visits

We are seeking an experienced Digital Designer / RTL Design Engineer to support the design and development of low-power, multi-clock-domain digital blocks within a distributed engineering team.

The engagement is expected to run from early November 2026 through September 2027. An initial 1-2 week ramp-up/onboarding period at the beginning of the assignment would be preferred. There may also be a requirement for one or two short on-site meetings during the engagement, potentially around the mid-term/design review. These would be one-off visits rather than ongoing travel requirements.

The engineer will be responsible for the design, implementation, integration, and sign-off support of low-power, multi-clock-domain digital blocks.

• Write the block specification in DOORs based on the system architecture and requirements.
• Participate in the microarchitecture definition, architecture refinement.
• Participate in design reviews.
• Develop low-power RTL design in VHDL/System Verilog according to the block specification, including block integration to the system. Emphasis in the project is on the aggressive application of low-power synchronous design technique and area reduction.
• Optimize the design for power, area, timing, and maintainability.
• Cooperate with the Verification team, do block debugging, specify corner cases for testcases and verification, support the coverage closure.
• Synthesize the block in Fusion Compiler including SDC writing, cooperate with the backend team
• Execute and debug LINT, CDC analysis, Formality Logical Equivalence Checking.

Required competencies

• Team player, strong communication skills in English (remote work in a distributed team), ability to drive issues to closure.
• System-level thinking, ability to choose the right trade-off.
• Ability to develop well-readable, reusable, and parametrized RTL code.
• SystemVerilog, VHDL RTL - sound knowledge.
• Low power digital design, experience with multiple clock domain designs, CDC techniques
• PSL, SVA assertions - applications in the digital design
• Fusion Compiler scripting, work in, constraining, SDC, STA review and block optimization
• DFT-friendly digital design, basics of the RTL DFT, functional testing, Formality/LEC.
• Experience with serial intefaces (SPI, I2C, I3C) (optional, but would be very useful to have)
• Digital design for signal processing (optional)
• GIT, SVN
• Jasper Gold tools - CDC (+RDC), LINTing (optional)
• DOORs - requirement management (optional)
• Python (optional)