Senior RTL Architect for AI Accelerators

Evollabs Tech; Dubai; On-site; AED 400,000 - 640,000; Full time

Job summary

Evollabs Tech in Dubai is seeking an experienced RTL designer to own end-to-end ASIC subsystems, from specification through post-silicon validation. You will craft production-grade RTL in Verilog/SystemVerilog and drive interface definitions across PCIe, Ethernet, and UCIe.

You will collaborate with silicon architects and verification engineers to meet PPA targets, implement robust DFT strategies, and maintain high-quality code for scalable AI workloads in production silicon.

Qualifications

• 7+ years of RTL design and ASIC development (Verilog/SystemVerilog preferred).
• Experience with chip development process and front-end tools/methodologies.
• Experience with complex IP integration (multi-core CPUs, NOCs, GPUs/NPUs, PCIe, 100/400G Ethernet, UCIe).
• Experience writing specifications and translating them into design.
• Experience with multiple clock domains and asynchronous interfaces.
• Familiarity with AMBA (AXI, AHB, APB).

Responsibilities

• Own ASIC subsystems end-to-end: spec, architectural exploration, IP evaluation/selection, integration, verification planning, and post-silicon validation.
• Define interfaces and write production RTL (Verilog/SystemVerilog).
• Verify at block and subsystem levels; set coverage goals and sign-off.
• Develop constraints and close timing; author SDC, run STA, CDC/RDC analyses, collaborate on floorplanning/CTS.
• Simulate and emulate (FPGA/emulator); debug waveforms/logs; correlate pre-/post-silicon behavior.
• Define and implement DFT/DFD (scan, MBIST/LBIST, boundary scan/JTAG); support ATPG and test bring-up.
• Maintain code quality; drive ECOs; lint, CDC/RDC, LEC, synthesis-friendly design practices.
• Build timing/debug automation: Tcl/PrimeTime scripts for skew analysis, clock dividers/special clocks, and core-to-IO interfaces (PCIe, 400GE, UCIe).
• Document specifications, micro-architecture, interfaces, and user guides for downstream teams.

Skills

RTL design

ASIC development

Verilog/SystemVerilog

UVM

IP integration

front-end tools

clock-domain crossing

PCIe/100/400G Ethernet/UCIe

AMBA (AXI/AHB/APB)

Tools

PrimeTime

Job description

Evollabs Tech in Dubai is seeking an experienced RTL designer to own end-to-end ASIC subsystems, from specification through post-silicon validation. You will craft production-grade RTL in Verilog/SystemVerilog and drive interface definitions across PCIe, Ethernet, and UCIe.

You will collaborate with silicon architects and verification engineers to meet PPA targets, implement robust DFT strategies, and maintain high-quality code for scalable AI workloads in production silicon.