Dubai-Based Senior AI SoC Physical Design Lead

Evollabs Tech; Dubai; On-site; AED 300,000 - 420,000; Full time

Job summary

Evollabs Tech in Dubai, UAE, is seeking a Senior Physical Design Engineer to drive physical implementation of AI SoC/ASIC accelerator designs. You will own blocks from RTL to GDS, lead floorplanning, placement, CTS, routing, timing closure, and signoff, collaborating closely with RTL, verification, DFT, architecture, and packaging teams.

The ideal candidate has 7+ years of hands-on ASIC/SoC physical design experience and proficiency with industry tools such as ICC2, Fusion, PrimeTime, Innovus,

Qualifications

• 7+ years of hands-on ASIC/SoC physical design experience.
• Experience taking complex blocks through physical signoff.
• Strong knowledge of floorplanning, PnR, CTS, STA, ECO, and signoff flows.
• Experience with advanced-node, high-frequency, or high-density designs.
• Proficiency with industry-standard EDA tools listed above.
• Strong scripting in Tcl/Python or shell.

Responsibilities

• Own block-level or subsystem physical design from netlist to GDS.
• Drive floorplanning, placement, CTS, routing, optimization, ECOs, and signoff.
• Develop floorplans for compute clusters, memory subsystems, NoCs, clocking structures, and high-speed blocks.
• Close timing across modes and corners, including generated clocks and SI-aware timing.
• Optimize designs for performance, power, area, routability, and manufacturability.
• Support power planning, IR drop, EM, extraction, and reliability closure.
• Execute physical verification (DRC/LVS/antenna/ERC/density).
• Collaborate with RTL, architecture, verification, DFT, and packaging teams.
• Integrate complex IPs such as NoC, CPU, GPU/NPU, PCIe, Ethernet, UCIe, HBM/GDDR.
• Develop scripts/methodologies to improve implementation efficiency and design quality.

Skills

ASIC/SoC physical design

Floorplanning

Place-and-route

Timing closure

RTL/verification collaboration

Scripting: Tcl/Python

Cross-functional teamwork

Education

Bachelor's degree in EE/CS

Tools

Synopsys ICC2/Fusion Compiler

PrimeTime

StarRC

Cadence Innovus

Tempus

Voltus

Calibre

Job description

Evollabs Tech in Dubai, UAE, is seeking a Senior Physical Design Engineer to drive physical implementation of AI SoC/ASIC accelerator designs. You will own blocks from RTL to GDS, lead floorplanning, placement, CTS, routing, timing closure, and signoff, collaborating closely with RTL, verification, DFT, architecture, and packaging teams.

The ideal candidate has 7+ years of hands-on ASIC/SoC physical design experience and proficiency with industry tools such as ICC2, Fusion, PrimeTime, Innovus,