Senior DFT Engineer for AI SoC/ASIC Test & Bring-Up

Evollabs Tech; Dubai; On-site; AED 420,000 - 660,000; Full time

Job summary

Evollabs Tech in Dubai is seeking a Senior DFT Engineer to own design-for-test architecture, verification, and silicon bring-up for advanced AI SoC / ASIC accelerator designs.

This role will work across RTL, verification, physical design, product engineering, ATE, and external partners to deliver testable, diagnosable, production-ready silicon.

Join us to ensure first silicon is testable, diagnosable, and production-ready, with a focus on MBIST/LBIST, boundary scan, and pattern delivery.

Qualifications

• 7+ years of hands-on DFT experience in ASIC or SoC development.
• Expert in scan insertion, ATPG, scan compression, fault coverage.
• Experience with MBIST, LBIST, JTAG, boundary scan, and test access architecture.
• Strong understanding of scan shift/capture timing and multi-clock-domain DFT.
• Experience debugging DFT across RTL, gate-level simulation, synthesis, STA, and silicon bring-up.
• Experience with complex SoC/IP integration and high-speed interfaces.
• Proficiency with Tessent, TestMAX/DFT Compiler, Modus or equivalents.
• Scripting in Tcl/Python/Perl/shell.
• Excellent communication and cross-functional collaboration.

Responsibilities

• Define and implement DFT architectures for AI SoC/ASIC blocks.
• Own scan insertion, ATPG, fault coverage, and DFT signoff.
• Implement and support MBIST, LBIST, JTAG, and memory test features.
• Develop DFT specifications, test plans, coverage targets, and signoff criteria.
• Collaborate with RTL and verification to bake in DFT early.
• Coordinate with physical design on timing, ECOs, and test closure.
• Debug DFT issues across RTL, gate-level sim, synthesis, and silicon bring-up.
• Support ATE pattern delivery, silicon debug, diagnostics, and yield learning.
• Build scripts to automate DFT implementation and reporting.

Skills

DFT engineering

Scan insertion

ATPG

MBIST/LBIST

Tcl/Python scripting

High-speed interfaces

SoC/Silicon debugging

NoC/CPU/GPU/NPU interfaces

Tools

Siemens Tessent

Synopsys TestMAX/DFT Compiler

Cadence Modus

Job description

Evollabs Tech in Dubai is seeking a Senior DFT Engineer to own design-for-test architecture, verification, and silicon bring-up for advanced AI SoC / ASIC accelerator designs.

This role will work across RTL, verification, physical design, product engineering, ATE, and external partners to deliver testable, diagnosable, production-ready silicon.

Join us to ensure first silicon is testable, diagnosable, and production-ready, with a focus on MBIST/LBIST, boundary scan, and pattern delivery.