RTL Developer (Dubai Office)

Evollabs Tech; Dubai; On-site; AED 400,000 - 640,000; Full time

Job summary

Evollabs Tech in Dubai is seeking an experienced RTL designer to own end-to-end ASIC subsystems, from specification through post-silicon validation. You will craft production-grade RTL in Verilog/SystemVerilog and drive interface definitions across PCIe, Ethernet, and UCIe.

You will collaborate with silicon architects and verification engineers to meet PPA targets, implement robust DFT strategies, and maintain high-quality code for scalable AI workloads in production silicon.

Qualifications

• 7+ years of RTL design and ASIC development (Verilog/SystemVerilog preferred).
• Experience with chip development process and front-end tools/methodologies.
• Experience with complex IP integration (multi-core CPUs, NOCs, GPUs/NPUs, PCIe, 100/400G Ethernet, UCIe).
• Experience writing specifications and translating them into design.
• Experience with multiple clock domains and asynchronous interfaces.
• Familiarity with AMBA (AXI, AHB, APB).

Responsibilities

• Own ASIC subsystems end-to-end: spec, architectural exploration, IP evaluation/selection, integration, verification planning, and post-silicon validation.
• Define interfaces and write production RTL (Verilog/SystemVerilog).
• Verify at block and subsystem levels; set coverage goals and sign-off.
• Develop constraints and close timing; author SDC, run STA, CDC/RDC analyses, collaborate on floorplanning/CTS.
• Simulate and emulate (FPGA/emulator); debug waveforms/logs; correlate pre-/post-silicon behavior.
• Define and implement DFT/DFD (scan, MBIST/LBIST, boundary scan/JTAG); support ATPG and test bring-up.
• Maintain code quality; drive ECOs; lint, CDC/RDC, LEC, synthesis-friendly design practices.
• Build timing/debug automation: Tcl/PrimeTime scripts for skew analysis, clock dividers/special clocks, and core-to-IO interfaces (PCIe, 400GE, UCIe).
• Document specifications, micro-architecture, interfaces, and user guides for downstream teams.

Skills

RTL design

ASIC development

Verilog/SystemVerilog

UVM

IP integration

front-end tools

clock-domain crossing

PCIe/100/400G Ethernet/UCIe

AMBA (AXI/AHB/APB)

Tools

PrimeTime

Job description

Your Mission

Own the end-to-end design of critical ASIC subsystems—from PLLs and compute clusters to interconnects and multi-die orchestration. The RTL you build becomes production silicon and moves real AI workloads faster. This is where microseconds, watts, and millimeters directly impact AI economics at scale.

Responsibilities

• Own complex ASIC subsystems end-to-end: specification, architectural exploration, IP evaluation/selection, integration, verification planning, and post-silicon validation
• Make architecture/micro-architecture trade-offs across features, performance, power, and area; define clean interfaces and write production-quality RTL (Verilog/SystemVerilog).
• Implement and verify at block and subsystem levels (UVM/formal where appropriate); set coverage goals and drive sign-off.
• Develop constraints and close timing: author SDC, run STA (setup/hold, OCV/derates), perform CDC/RDC analysis, and collaborate with PD on floorplanning and CTS.
• Simulate and emulate (FPGA/emulator), debug waveforms/logs, and correlate pre-/post-silicon behavior.
• Define and implement DFT/DFD (scan, MBIST/LBIST, boundary scan/JTAG); support ATPG and test bring-up.
• Maintain code quality with lint, CDC/RDC, LEC, and synthesis-friendly design practices; drive ECOs as needed.
• Build timing/debug automation: create Tcl/PrimeTime scripts for skew analysis, clock dividers/special clocks, and core-to-IO interfaces (PCIe, 400GE, UCIe).
• Document clearly: specifications, micro-architecture, interfaces, and user guides for downstream teams.

You’ll Collaborate With

Our silicon architects designing the next breakthrough in AI compute, verification engineers, Linux driver and firmware engineers building the software stack, security teams protecting customer assets, compiler and ML framework teams optimizing workload mapping, and system validation engineers ensuring enterprise reliability — together, we're building the infrastructure that makes AI accessible and powerful.

Minimum Qualifications

• 7+ years of experience in RTL design and ASIC development (verilog/systemverilog is preferred)
• Hands-on experience in all aspects of the chip development process with proficiency in front end tools and methodologies
• Experience with configuration and integration of a complex IPs is a must (at least one of the following: multi-core CPUs, NOCs, custom accelerators aka GPU/NPU or high-speed interfaces like PCIe, 100/400G Ethernet, UCIe)
• Experience writing specifications and converting them into design
• Experience with multiple clock domains and asynchronous interfaces
• Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB)

Preferred (Nice-to-Haves)

• Experience with power and clock management designs
• Formal Equivalency Checking RTL to Netlist
• Experience with DFT
• Understanding of AI accelerator architectures (systolic arrays, dataflow, tiling) and memory bandwidth optimization
• Experience with HBM/GDDR integration or other high-bandwidth memory subsystems

What Success Really Means

• First silicon boots and runs real AI workloads (not just benchmarks)
• PPA targets met: performance/watt competitive with industry leaders
• Compiler team can generate efficient code without hardware workarounds

Mean time to debug customer issues:

Ready to accelerate the future of AI?

Join us in our mission to democratize AI compute — where your RTL expertise becomes the bedrock of tomorrow's AI breakthroughs.