Senior Package Design Engineer - AI Accelerator Packaging

Evollabs Tech; Dubai; On-site; AED 240,000 - 360,000; Full time

Job summary

Evollabs Tech in Dubai, United Arab Emirates, seeks an experienced Package Design Engineer to own the processor package for AI accelerators from concept to silicon. You will drive packaging choices, substrate/interposer design, and test plans in collaboration with silicon, board, and SI/PI teams.

Responsibilities include high-speed interconnects, PDN/thermal strategy, and coordinating with foundries and OSATs to ensure manufacturability and performance.

Qualifications

• 8+ years in semiconductor package design for high-performance devices.
• Experience with 2.5D interposers, CoWoS, EMIB, InFO/FoCoS.
• Proven track record taking multi-chiplet packages to production.
• Experience with PCIe Gen5/Gen6 and 400/800G Ethernet.
• Experience with die-to-die interconnects (UCIe, BoW).
• HBM memory subsystem routing and integration.
• Strong signal and power integrity expertise.
• Thermal-mechanical design and PDN experience.
• Package test and first-silicon bring-up involvement.

Responsibilities

• Define package architecture and technology selection.
• Own substrate and interposer design for multi-die assemblies.
• Deliver high-speed interface packaging meeting PCIe Gen5/Gen6, 400/800G Ethernet.
• Define PDN, decoupling, and thermal solution.
• Engage foundries, OSATs, and substrate suppliers.
• Define package test plans and support first-silicon bring-up.
• Lead design reviews across silicon, board, SI/PI teams.

Skills

Semiconductor package design

High-performance ASICs/GPUs/AI acceler

2.5D interposer

CoWoS/EMIB/InFO

D2D interconnects

HBM interconnects

Signal integrity

Power integrity

PDN design

Thermal-mechanical design

Package EDA tools

Ansys HFSS/SIwave

Education

Bachelor's or Master's in Electrical Engineering

Tools

Cadence APD/SiP Layout

Synopsys 3DIC Compiler

Job description

Evollabs Tech in Dubai, United Arab Emirates, seeks an experienced Package Design Engineer to own the processor package for AI accelerators from concept to silicon. You will drive packaging choices, substrate/interposer design, and test plans in collaboration with silicon, board, and SI/PI teams.

Responsibilities include high-speed interconnects, PDN/thermal strategy, and coordinating with foundries and OSATs to ensure manufacturability and performance.