Senior ASIC Verification Architect

Evollabs Tech; Dubai; On-site; AED 350,000 - 550,000; Full time

Job summary

Evollabs Tech in Dubai seeks an experienced ASIC/SoC verification engineer to own end-to-end verification of critical subsystems, architect UVM environments, and map specs to assertions and checkers for fast tape-out.

You will co-sim with firmware, run emulation/FPGA prototypes, and drive coverage to closure using SystemVerilog/UVM, SVA, and industry simulators, collaborating with RTL, firmware, and DFT teams.

Qualifications

• 7+ years in ASIC/SoC verification with SystemVerilog/UVM from test plan to sign-off.
• Strong command of constrained-random stimulus, scoreboarding, coverage-driven verification, and SVA.
• Hands‑on with major simulators (VCS/Questa/Xcelium) and regression/CI tooling.
• Familiarity with standard protocols (AMBA, AXI, APB, AHB) and industrial VIPs
• Experience verifying complex IP/subsystems (multi-core compute, NoC/coherency, PCIe/Ethernet/HBM/DDR/UCIe).
• Proficient in scripting for automation (Python/TCL/Make) and building reusable verification components.
• Solid understanding of SoC fundamentals: resets, clocking, CDC/RDC, back‑pressure/flow control, performance counters.

Responsibilities

• Own block-to-subsystem verification: author verification plans from specs, define stimulus/coverage strategy, and deliver sign-off with data (functional/code/assertion coverage).
• Build scalable UVM environments: agents, monitors, scoreboards, sequences, reference models (C++/Python/DPI), protocol checkers, and reusable components.
• Exercise real workloads: co-sim with firmware/drivers, run emulation/FPGA prototypes, and correlate performance/behavior with architectural models.
• Apply assertions & formal: write SVA, run formal where appropriate (protocol/liveness/safety), and integrate results into overall coverage.
• Close quality gates: lint/CDC/RDC verification collaboration, gate-level/reset/power-up scenarios, low‑power (UPF) intent checks.
• Harden regressions: own CI pipelines, randomized/constrained tests, triage failures, root‑cause with RTL/design, and track fixes to closure.
• Interface & document: keep specs, test plans, coverage dashboards, and bug reports clear for Architects, RTL, Firmware/Drivers, and DFT/PD teams.

Skills

SystemVerilog/UVM

Constrained-random stimulus

Scoreboarding

SVA

CI tooling

Python scripting

RTL collaboration

Tools

VCS

Questa

Xcelium

Python

TCL

Make

Job description

Evollabs Tech in Dubai seeks an experienced ASIC/SoC verification engineer to own end-to-end verification of critical subsystems, architect UVM environments, and map specs to assertions and checkers for fast tape-out.

You will co-sim with firmware, run emulation/FPGA prototypes, and drive coverage to closure using SystemVerilog/UVM, SVA, and industry simulators, collaborating with RTL, firmware, and DFT teams.