Senior Physical Design Engineer

Evollabs Tech; Dubai; On-site; AED 300,000 - 420,000; Full time

Job summary

Evollabs Tech in Dubai, UAE, is seeking a Senior Physical Design Engineer to drive physical implementation of AI SoC/ASIC accelerator designs. You will own blocks from RTL to GDS, lead floorplanning, placement, CTS, routing, timing closure, and signoff, collaborating closely with RTL, verification, DFT, architecture, and packaging teams.

The ideal candidate has 7+ years of hands-on ASIC/SoC physical design experience and proficiency with industry tools such as ICC2, Fusion, PrimeTime, Innovus,

Qualifications

• 7+ years of hands-on ASIC/SoC physical design experience.
• Experience taking complex blocks through physical signoff.
• Strong knowledge of floorplanning, PnR, CTS, STA, ECO, and signoff flows.
• Experience with advanced-node, high-frequency, or high-density designs.
• Proficiency with industry-standard EDA tools listed above.
• Strong scripting in Tcl/Python or shell.

Responsibilities

• Own block-level or subsystem physical design from netlist to GDS.
• Drive floorplanning, placement, CTS, routing, optimization, ECOs, and signoff.
• Develop floorplans for compute clusters, memory subsystems, NoCs, clocking structures, and high-speed blocks.
• Close timing across modes and corners, including generated clocks and SI-aware timing.
• Optimize designs for performance, power, area, routability, and manufacturability.
• Support power planning, IR drop, EM, extraction, and reliability closure.
• Execute physical verification (DRC/LVS/antenna/ERC/density).
• Collaborate with RTL, architecture, verification, DFT, and packaging teams.
• Integrate complex IPs such as NoC, CPU, GPU/NPU, PCIe, Ethernet, UCIe, HBM/GDDR.
• Develop scripts/methodologies to improve implementation efficiency and design quality.

Skills

ASIC/SoC physical design

Floorplanning

Place-and-route

Timing closure

RTL/verification collaboration

Scripting: Tcl/Python

Cross-functional teamwork

Education

Bachelor's degree in EE/CS

Tools

Synopsys ICC2/Fusion Compiler

PrimeTime

StarRC

Cadence Innovus

Tempus

Voltus

Calibre

Job description

About UsWe are a tech company specializing in the design and development of cutting‑edge, customized server hardware solutions optimized for artificial intelligence and machine learning applications. Our mission is to empower businesses and researchers to accelerate their AI initiatives by providing them with high‑performance, scalable, and energy‑efficient hardware infrastructure.

Location: Dubai - UAE

Team: SoC Physical Design Team

Type: Full-time – On-site

Role Overview

We are seeking a Senior Physical Design Engineer to drive physical implementation of advanced AI SoC / ASIC accelerator designs. This role will own complex blocks and subsystems from RTL/netlist handoff through floorplanning, place‑and‑route, timing closure, physical verification, and signoff.

The ideal candidate has strong experience with advanced‑node physical design, production tapeouts, PPA optimization, and cross‑functional execution across RTL, verification, DFT, architecture, and signoff teams.

Responsibilities

• Own block-level or subsystem-level physical design from netlist to GDS.
• Drive floorplanning, placement, CTS, routing, optimization, ECOs, and signoff closure.
• Develop floorplans for compute clusters, memory subsystems, NoCs, clocking structures, and high‑speed interface blocks.
• Close timing across multiple modes and corners, including setup, hold, skew, generated clocks, and SI‑aware timing.
• Optimize designs for performance, power, area, routability, and manufacturability.
• Support power planning, IR drop, EM, extraction, and reliability closure.
• Execute physical verification, including DRC, LVS, antenna, ERC, density, and metal fill.
• Collaborate with RTL, architecture, verification, DFT, and packaging, teams to resolve implementation issues.
• Support integration of complex IPs such as NoC, PCIe, Ethernet, UCIe, HBM/GDDR, PLLs, CPUs, GPUs, NPUs, or custom AI accelerators.
• Develop scripts and methodology improvements to improve implementation efficiency, reporting, and design quality.

Minimum Qualifications

• 7+ years of hands‑on experience in ASIC or SoC physical design.
• Experience taking complex blocks or subsystems through physical signoff.
• Strong knowledge of floorplanning, place‑and‑route, CTS, STA, ECO, and signoff flows.
• Experience with advanced‑node, high-frequency, or high‑density designs.
• Strong understanding of SDC, setup/hold timing, multi‑mode multi‑corner analysis, and clock‑tree optimization.
• Experience with physical verification and signoff, including DRC, LVS, IR drop, EM, and extraction.
• Experience integrating complex IPs such as NoC, CPU, GPU/NPU, PCIe, Ethernet, UCIe, HBM/GDDR, or other high‑speed interfaces.
• Familiarity with multiple clock domains, asynchronous interfaces, generated clocks, and PLL integration.
• Proficiency with industry‑standard EDA tools such as Synopsys ICC2/Fusion Compiler, PrimeTime, StarRC, Cadence Innovus, Tempus, Voltus, RedHawk, Calibre, or equivalent.
• Strong scripting skills in Tcl, Python, Perl, or shell.
• Strong debugging, communication, and cross‑functional collaboration skills.

Preferred Qualifications

• Experience with AI accelerators, GPUs, NPUs, or highly parallel compute architectures.
• Experience with HBM/GDDR, chiplets, UCIe, 2.5D packaging, or package‑aware physical design.
• Experience with DFT‑aware physical implementation, scan reordering, MBIST/LBIST, and test‑mode timing.
• Prior tapeout experience on advanced‑node SoCs.

What Success Really Means

• First silicon boots and runs real AI workloads, not just benchmarks.
• PPA targets are met, with performance per watt competitive with industry leaders.
• Timing, power, physical verification, and reliability signoff are completed with high quality and predictable execution.
• Compiler, firmware, and system teams can use the hardware efficiently without physical‑design‑driven workarounds.
• Critical silicon or customer issues can be debugged and root‑caused quickly, with a target mean time to debug of less than 24 hours.