Senior AI Accelerator Networking Engineer

Evollabs Tech; Dubai; On-site; AED 300,000 - 540,000; Full time

Job summary

Evollabs Tech in Dubai is seeking an experienced AI infrastructure engineer to design and implement high-performance collective communication for AI accelerators and heterogeneous NPU-GPU systems. You will work at the intersection of accelerator runtime, networking, and distributed AI workloads to enable scalable, low-latency inference across multi-chip rack-scale deployments.

You will develop runtime components for device discovery, rank management, and synchronization, while optimizing

Qualifications

• Strong C/C++ and Python programming skills with experience building low-level runtime, driver, networking, or distributed systems software.
• Deep understanding of collective communication primitives (AllReduce, ReduceScatter, AllGather, AllToAll, Broadcast, Send/Recv, Barrier).
• Experience with accelerator runtime concepts like queues, streams, events, and memory management.

Responsibilities

• Design and implement collective communication primitives for AI accelerators.
• Build NPU-native CCL support for multi-chip and rack-scale AI inference systems.
• Design and implement heterogeneous NPU-GPU communication paths for distributed AI workloads.
• Develop communication runtime components for device discovery, rank management, topology awareness, and synchronization.
• Integrate transport-layer across PCIe, Ethernet/RDMA, custom accelerator fabrics.
• Collaborate with hardware, runtime, compiler, and model-serving teams to co-design scalable communication paths for AI workloads.
• Profile, debug, and optimize communication bottlenecks including bandwidth and latency.
• Build tests for multi-device and heterogeneous communication scenarios.

Skills

C/C++

Python

Runtime dev

Distributed systems

Networking

Performance engineering

GPU/ NPU memory

Education

MS/PhD in CS/CE

Tools

NCCL

MPI

UCX

libfabric

Job description

Evollabs Tech in Dubai is seeking an experienced AI infrastructure engineer to design and implement high-performance collective communication for AI accelerators and heterogeneous NPU-GPU systems. You will work at the intersection of accelerator runtime, networking, and distributed AI workloads to enable scalable, low-latency inference across multi-chip rack-scale deployments.

You will develop runtime components for device discovery, rank management, and synchronization, while optimizing