Senior RISC-V AI Accelerator Architect

Evollabs; Dubai; On-site; AED 180,000 - 360,000; Full time

Job summary

Evollabs seeks a senior RISC-V Architect to own the architecture of our AI accelerator core. You will define the base ISA, vector/matrix extensions, and the per-core microarchitecture, shaping silicon from ISA to RTL.

You will design NoC topology, memory data paths, and end-to-end data flows, and ensure the compiler and toolchain contracts align with RTL and verification. You will collaborate with RTL, verification, and performance teams in Dubai.

Qualifications

• Bachelor's or Master's in a related engineering field.
• 10+ years in CPU/DSP/NPU/IP architecture from ISA to silicon.
• Deep expertise in RISC-V base ISA and extensions.
• Hands-on SystemVerilog experience with RTL and testbenches.

Responsibilities

• Define base ISA, privilege modes, and scalar pipeline scope.
• Own RVV and AME matrix extensions architecture and encodings.
• Design NoC and cluster architecture including mesh and routing.
• Architect per-core SRAM/scratchpad, DMA engines and data flows.
• Provide golden model specifications and drive engineering reviews.

Skills

RISC-V

SystemVerilog

C/C++

Performance modelling

NoC architecture

ISA definition

RTL integration

Education

Bachelor's or Master's in Computer Engineering, Electrical Engineering, or Computer Science

Tools

Verilator

riscv-dv

cocotb

Job description

Evollabs seeks a senior RISC-V Architect to own the architecture of our AI accelerator core. You will define the base ISA, vector/matrix extensions, and the per-core microarchitecture, shaping silicon from ISA to RTL.

You will design NoC topology, memory data paths, and end-to-end data flows, and ensure the compiler and toolchain contracts align with RTL and verification. You will collaborate with RTL, verification, and performance teams in Dubai.