Senior DFT Engineer - AI SoC Test & Bring-Up

Evollabs; Dubai; On-site; AED 400,000 - 700,000; Full time

Job summary

Evollabs is seeking a Senior DFT Engineer in Dubai to own design-for-test architecture, verification, and silicon bring-up for advanced AI SoC/ASIC accelerators. You will collaborate across RTL, verification, physical design, and external partners to deliver testable, production-ready silicon.

Ideal candidates have 7+ years in DFT, strong experience with scan/insertion, ATPG, MBIST/LBIST, and multi-clock-domain testing, plus expertise with Tessent, TestMAX/DFT Composer, and Cadence tools.

Qualifications

• 7+ years of hands-on DFT experience in ASIC/SoC development.
• Strong experience with scan insertion, ATPG, scan compression, fault simulation, and coverage closure.
• Experience with MBIST, LBIST, JTAG, boundary scan, and test access architecture.
• Understanding of scan shift/capture timing, at-speed testing, test-mode constraints, and multi-clock-domain DFT.
• Experience debugging DFT issues across RTL, gate-level simulation, synthesis, STA, ATPG, and silicon bring-up.
• Experience with complex SoC/IP integration (NoC, CPU/GPU/NPU, PCIe, Ethernet, UCIe, HBM/GDDR).
• Proficiency with DFT tools (Siemens Tessent, Synopsys, Cadence).
• Strong scripting skills in Tcl, Python, Perl, or shell.
• Excellent written and verbal communication for cross-functional teams.

Responsibilities

• Define and implement DFT architectures for complex AI SoC/ASIC blocks and subsystems.
• Own scan insertion, scan compression, ATPG, fault coverage closure, and DFT signoff.
• Implement and support MBIST, LBIST, JTAG, boundary scan, test access, and memory repair features.
• Develop DFT specifications, test plans, coverage targets, constraints, and signoff criteria.
• Work with RTL and verification teams to ensure DFT requirements are built into the design early.
• Collaborate with physical design teams on scan reordering, test-mode timing, congestion, ECOs, and implementation closure.
• Debug DFT issues across RTL, gate-level simulation, synthesis, STA, ATPG, and silicon bring-up.
• Support ATE pattern delivery, silicon debug, diagnostics, yield learning, and production test ramp.
• Communicate DFT status, risks, trade-offs, and signoff readiness clearly with internal teams, external partners, vendors, and stakeholders.
• Build scripts and automation to improve DFT implementation, reporting, pattern generation, and debug

Skills

DFT

ASIC/SoC dev

ATPG

MBIST/LBIST

JTAG/boundary

Scripting (Tcl/Python)

Communication

Education

Bachelor's in Electrical Engineering

Tools

Siemens Tessent

Synopsys TestMAX/DFT Compiler

Cadence Modus

Job description

Evollabs is seeking a Senior DFT Engineer in Dubai to own design-for-test architecture, verification, and silicon bring-up for advanced AI SoC/ASIC accelerators. You will collaborate across RTL, verification, physical design, and external partners to deliver testable, production-ready silicon.

Ideal candidates have 7+ years in DFT, strong experience with scan/insertion, ATPG, MBIST/LBIST, and multi-clock-domain testing, plus expertise with Tessent, TestMAX/DFT Composer, and Cadence tools.