Package Design Engineer

Evollabs Tech; Dubai; On-site; AED 240,000 - 360,000; Full time

Job summary

Evollabs Tech in Dubai, United Arab Emirates, seeks an experienced Package Design Engineer to own the processor package for AI accelerators from concept to silicon. You will drive packaging choices, substrate/interposer design, and test plans in collaboration with silicon, board, and SI/PI teams.

Responsibilities include high-speed interconnects, PDN/thermal strategy, and coordinating with foundries and OSATs to ensure manufacturability and performance.

Qualifications

• 8+ years in semiconductor package design for high-performance devices.
• Experience with 2.5D interposers, CoWoS, EMIB, InFO/FoCoS.
• Proven track record taking multi-chiplet packages to production.
• Experience with PCIe Gen5/Gen6 and 400/800G Ethernet.
• Experience with die-to-die interconnects (UCIe, BoW).
• HBM memory subsystem routing and integration.
• Strong signal and power integrity expertise.
• Thermal-mechanical design and PDN experience.
• Package test and first-silicon bring-up involvement.

Responsibilities

• Define package architecture and technology selection.
• Own substrate and interposer design for multi-die assemblies.
• Deliver high-speed interface packaging meeting PCIe Gen5/Gen6, 400/800G Ethernet.
• Define PDN, decoupling, and thermal solution.
• Engage foundries, OSATs, and substrate suppliers.
• Define package test plans and support first-silicon bring-up.
• Lead design reviews across silicon, board, SI/PI teams.

Skills

Semiconductor package design

High-performance ASICs/GPUs/AI acceler

2.5D interposer

CoWoS/EMIB/InFO

D2D interconnects

HBM interconnects

Signal integrity

Power integrity

PDN design

Thermal-mechanical design

Package EDA tools

Ansys HFSS/SIwave

Education

Bachelor's or Master's in Electrical Engineering

Tools

Cadence APD/SiP Layout

Synopsys 3DIC Compiler

Job description

Location: Dubai - UAE
Team: Hardware Engineering - Package Design & Bring-Up
Type: Full-time - On-site

About Us

We are a tech company specializing in the design and development of cutting-edge, customized server hardware solutions optimized for artificial intelligence and machine learning applications. Our mission is to empower businesses and researchers to accelerate their AI initiatives by providing them with high-performance, scalable, and energy-efficient hardware infrastructure. As a rapidly growing company at the forefront of AI hardware innovation, we are constantly seeking talented and motivated individuals to join our team. We offer a dynamic and challenging work environment, with opportunities to make a significant impact on the future of AI technology.

Your Mission

As a Package Design Engineer, you will own the chip package of our AI accelerators end to end, from packaging technology selection and die/package/board co-design through substrate and interposer design, package-level test, and first-silicon bring-up. You will turn multi-chiplet silicon with demanding high-speed interfaces into robust, manufacturable, high-performance packages, working at the intersection of silicon design, signal and power integrity, thermal-mechanical engineering, and the foundry/OSAT supply chain.

Responsibilities

• Package architecture and technology selection: evaluate standard flip-chip BGA and advanced packaging options (2.5D silicon interposer, silicon bridge, fan-out, 3D stacking) against product requirements, and drive die/package/board co-optimization of floorplans, bump patterns, pad rings, and ball-out with silicon and system teams.
• Multi-chiplet package design: own substrate and interposer design for multi-die assemblies, including netlist management, routing, layer stack-up definition, and design-rule compliance across compute, memory, and I/O chiplets.
• High-speed interface packaging: deliver package channels that meet the budgets of PCIe Gen5/Gen6, 400/800G Ethernet (56G/112G PAM4 SerDes), HBM, and UCIe/BoW die-to-die links, collaborating with signal and power integrity engineers on extraction, simulation, and margin sign-off.
• Power, thermal, and mechanical co-design: define the package PDN, decoupling strategy, and thermal solution for high-power accelerator silicon, and manage warpage, CTE mismatch, and reliability risks together with thermal-mechanical engineers.
• Manufacturing and supply-chain execution: engage foundries, OSATs, and substrate suppliers on design rules, DFM feedback, assembly flows, qualification, and yield improvement, and drive package NPI from tape-out to production release.
• Package test and silicon bring-up: define package-level test and characterization plans, support first-silicon bring-up in the lab, and lead package-related debug and failure analysis through to root cause and corrective action.
• Cross-functional collaboration and documentation: write clear package specifications, design guidelines, and review material, and lead design reviews with silicon, board, SI/PI, thermal, and product engineering teams.

Requirements

• Bachelor's or Master's in Electrical Engineering, Materials Science, Mechanical Engineering, or related field.
• 8+ years in semiconductor package design, with a strong focus on high-performance digital ASICs, GPUs, or AI accelerators.
• Proven track record of taking complex multi-chiplet packages (2.5D interposer, silicon bridge, or fan-out based) from concept to production.
• Hands-on experience with both standard flip-chip BGA and advanced packaging technologies such as CoWoS, EMIB, InFO/FoCoS, or equivalent foundry and OSAT platforms.
• Package design experience for high-speed serial interfaces, specifically PCIe Gen5/Gen6 and 400/800G Ethernet, including breakout, escape routing, and channel budget ownership.
• Experience with die-to-die interconnects such as UCIe or Bunch of Wires (BoW), including bump map definition, channel design, and routing rules for D2D links.
• Experience integrating HBM or similar memory subsystems on interposer or bridge, including routing, stack-up, and assembly considerations.
• Solid grounding in package signal and power integrity, transmission line theory, and PDN design, with the ability to drive and interpret extraction and simulation results.
• Working knowledge of thermal and mechanical fundamentals for large-body, high-power packages, including warpage control and JEDEC reliability qualification.
• Experience supporting package test, characterization, first-silicon bring-up, and failure analysis in collaboration with test and product engineering.
• Proficiency with package EDA tools such as Cadence APD/SiP Layout or Synopsys 3DIC Compiler, plus familiarity with SI/PI analysis tools (Ansys HFSS/SIwave, Cadence Clarity/Sigrity, or similar).
• Excellent cross-functional communication and documentation skills, including experience working directly with foundry, OSAT, and substrate vendor engineering teams.

Preferred Qualifications (Nice-to-Haves)

• Experience with 3D stacking and hybrid bonding technologies (SoIC, Foveros, or similar) and their design and test implications.
• Exposure to co-packaged optics or photonics packaging for high-bandwidth I/O.
• Experience defining packaging testchips and running technology qualification vehicles with foundry or OSAT partners.
• Hands-on use of thermal and mechanical simulation tools (Ansys Icepak, Celsius, mechanical FEA) for package-level analysis.
• Familiarity with UCIe compliance and interoperability testing, or participation in chiplet standards bodies (UCIe Consortium, OCP ODSA).
• Experience managing OSAT and substrate vendor relationships, schedules, and cost trade-offs during NPI.

Why Join Us

• Own the package of a next-generation AI accelerator from first concept to working silicon, where your decisions directly set the product's performance, power, and cost.
• Work in a tight cross-functional team of silicon, board, SI/PI, and thermal engineers that values technical depth and hands-on problem solving.
• Cover the full scope in one role: architecture, design, supplier engagement, lab bring-up, and production ramp.
• Competitive compensation, growth opportunities, and the chance to help define the platform that powers advanced AI workloads.