Senior AI SoC Physical Design Engineer

Evollabs; Dubai; On-site; AED 520,000 - 780,000; Full time

Job summary

Evollabs in Dubai seeks a Senior Physical Design Engineer to drive physical implementation of AI accelerators from RTL handoff through floorplanning, placement, routing, timing closure and signoff. You will own complex blocks, optimize PPA, and collaborate with RTL, verification, DFT, and packaging teams.

The ideal candidate has 7+ years in ASIC/SoC physical design, experience with multi‑corner timing, advanced-node processes, and hands‑on signoff.

Qualifications

• 7+ years of hands-on ASIC/SoC physical design experience.
• Experience taking complex blocks through physical signoff.
• Strong knowledge of floorplanning, P&R, CTS, STA, ECO, and signoff flows.
• Experience with advanced-node, high-frequency, or high-density designs.
• Understanding of SDC, setup/hold timing, and multi-mode multi-corner timing.
• Experience with DRC, LVS, IR drop, EM, and extraction.

Responsibilities

• Own block-level or subsystem physical design from netlist to GDS.
• Drive floorplanning, placement, CTS, routing, ECOs, and signoff closure.
• Develop floorplans for compute clusters, memory subsystems, NoCs and high-speed blocks.
• Close timing across modes and corners, including generated clocks.
• Optimize for performance, power, area, routability, and manufacturability.
• Support power planning, IR drop, EM, extraction, and reliability closure.
• Execute physical verification (DRC/LVS/antenna/ERC) and signoff.
• Collaborate with RTL, architecture, verification, DFT, and packaging teams.
• Integrate IPs like NoC, PCIe, Ethernet, UCIe, HBM/GDDR, CPUs, GPUs, NPUs.
• Develop scripts/methodologies to improve efficiency and design quality.

Skills

Floorplanning

Place-and-Route

CTS

STA

Signoff

PPA optimization

NoC

PCIe

Ethernet

UCIe

Tcl

Python

Perl

Shell

DFT-aware design

Tools

Synopsys ICC2

Fusion Compiler

PrimeTime

StarRC

Cadence Innovus

Tempus

Voltus

RedHawk

Calibre

Job description

Evollabs in Dubai seeks a Senior Physical Design Engineer to drive physical implementation of AI accelerators from RTL handoff through floorplanning, placement, routing, timing closure and signoff. You will own complex blocks, optimize PPA, and collaborate with RTL, verification, DFT, and packaging teams.

The ideal candidate has 7+ years in ASIC/SoC physical design, experience with multi‑corner timing, advanced-node processes, and hands‑on signoff.