RISC-V/NPU Architect

Evollabs Tech; Dubai; On-site; AED 500,000 - 900,000; Full time

Job summary

Evollabs Tech is seeking a senior RISC‑V Architect to own the architecture of our AI Accelerator— a many‑core compute cluster. You will define the base ISA, vector and matrix extensions, per‑core microarchitecture, and NoC topology shaping real AI workloads into RTL for tapeout.

Join a fast‑growing team building energy‑efficient, high‑performance hardware for AI applications, collaborating across RTL, verification, toolchain, and software to ensure silicon faithfulness to the spec.

Qualifications

• 10+ years in CPU/DSP/NPU IP architecture, from ISA to RTL.
• Deep expertise in the RISC-V base ISA, privilege modes, and extensions.
• Hands-on SystemVerilog experience with RTL and testbenches.
• Strong NoC/interconnect experience and performance reasoning.

Responsibilities

• Define base ISA, vector and matrix extensions, per-core microarchitecture.
• Design NoC topology, routing, DMA and data movement model.
• Specify memory/scratchpad, DMA engines, data flows between memory, NoC and cores.
• Own golden model, specs, and toolchain integration.

Skills

RISC-V arch

C/C++

SystemVerilog

NoC design

RVV

Matrix extensions

Perf modeling

Documentation

Cross-functional

Education

Engineering/CS degree

Tools

Verilator

riscv-dv

cocotb

MLIR/LLVM

Job description

Location: Dubai - UAE

Team: SoC Architecture – NPU Core & ISA

Type: Full-time – On-site

About Us

We are a tech company specializing in the design and development of cutting‑edge, customized server hardware solutions optimized for artificial intelligence and machine learning applications.

Our mission is to empower businesses and researchers to accelerate their AI initiatives by providing them with high‑performance, scalable, and energy‑efficient hardware infrastructure.

As a rapidly growing company at the front‑of‑line AI hardware innovation, we are constantly seeking talented and motivated individuals to join our team. We offer a dynamic and challenging work environment with opportunities to make a significant impact on the future of AI.

Your Mission

As a RISC‑V Architect, you will own the architecture of our AI Accelerator — a many‑core RISC‑V compute cluster. You will define the base ISA, the vector and matrix extensions, the per‑core microarchitecture, and the cluster/NoC topology that turn real AI training and inference workloads into synthesizable, verification‑ready RTL feeding our next‑generation silicon. You set the architectural contracts that RTL, verification, toolchain, and compiler teams build against, and drive the integration and microarchitecture reviews that keep silicon faithful to the spec.

Responsibilities

• RISC‑V core and ISA definition: define the base ISA, privilege modes, and scalar pipeline scope; specify the microarchitecture requirements that balance programmability, performance, and PPA.
• Vector and matrix extension architecture: own the RVV and AME matrix extensions — its register and accumulator model, instruction encodings in the custom‑opcode space, and the golden‑model semantics that define correct behavior.
• NoC and cluster architecture: design the on‑chip interconnect — mesh topology, routing, flow control, virtual channels, the DMA/data‑movement model, and how the cluster is represented to system software and the compiler.
• Memory and data‑movement co‑design: architect the per‑core SRAM/scratchpad, DMA engines, and end‑to‑end data flows between local memory, the NoC, and the compute cores datapaths to sustain persistent throughput.
• Golden model and specification ownership: produce microarchitecture and AME specifications and interface contracts, and own the golden reference model's behavior, providing RTL, DV, and toolchain teams with one authoritative reference to build and verify against.
• Compiler and toolchain contracts: define the ISA/ABI and the intrinsic/builtin surface that the compiler backend and AME code generation target, collaborating with the toolchain team on autovectorization, tiling, and code‑generation assumptions.
• Hands‑on microarchitecture and integration: prototype and pressure‑test critical blocks in SystemVerilog, and drive the integration and microarchitecture reviews across RTL, verification, compiler, performance, and physical‑design teams to keep implementation faithful to the spec from ISA definition through to taped‑out IP.

Requirements

• Bachelor's or Master's in Computer Engineering, Electrical Engineering, Computer Science, or related field.
• 10+ years in CPU, DSP, or NPU/accelerator IP architecture, with a proven track record of taking compute‑core IP from ISA definition through RTL to silicon.
• Deep expertise in the RISC‑V architecture — the base ISA, privilege modes, and the practice of defining and extending ISAs with custom, non‑standard instructions.
• Hands‑on experience with the RISC‑V Vector extension (RVV) or matrix/tensor extensions (AME or equivalent AI matrix engines), including register models, instruction encodings, and datapath implications.
• Strong grasp of NoC/interconnect architecture — mesh/torus topologies, routing, flow control, and virtual channels — with a clear feel for the latency, bandwidth, and area trade‑offs of an implementation.
• Solid microarchitecture skills: pipelines, memory hierarchy, DMA, coherency and memory ordering, and hazard handling, with the ability to reason quantitatively about PPA.
• Solid understanding of AI workloads (GEMM, conv‑as‑GEMM, attention) and how they stress compute, memory, and interconnect.
• Hands‑on SystemVerilog experience — writing and reviewing synthesizable RTL and testbenches, co‑simulating against a golden reference model, and driving coverage closure.
• Proficiency in C/C++ and scripting (Python, Bash); comfort with instruction‑set simulators, profilers, and performance modeling across the HW/SW boundary.
• Excellent cross‑functional communication and documentation skills; ability to write precise specifications and drive integration and microarchitecture reviews to architectural alignment with internal and external partners.

Preferred Qualifications (Nice‑to‑Haves)

• Direct experience with the RVV 1.0 and the emerging RISC‑V Matrix (AMEX/IME) draft specifications, or active participation in a RISC‑V working group.
• Experience with a taped‑out RISC‑V core or contributions to open‑hardware silicon.
• Familiarity with MLIR/LLVM compiler stacks and graph‑compilation flows (tiling, fusion, layout, quantization) for AI accelerators.
• Hands‑on with open‑source RISC‑V verification tooling (riscv‑arch‑test, riscv‑dv, cocotb, Verilator) and formal methods.
• Knowledge of chiplet/multi‑die integration and NoC‑to‑AXI/CHI fabric bridging.
• Experience with power/performance modeling and correlating pre‑silicon models to silicon behavior.

Why Join Us

• Own the architecture of a fully proprietary AI accelerator core — your ISA and microarchitecture decisions define silicon that we ship, not a derivative of someone else's IP.
• Work at the frontier of RISC‑V for AI: extend RVV and define a custom matrix engine on a fully open‑source toolchain, alongside RTL, verification, compiler, and physical‑design teams.
• Build the compute foundation that feeds our next‑generation accelerator tapeout, with hands‑on impact from spec to silicon.
• Competitive compensation, growth opportunities, and the chance to help define the platform that powers advanced AI workloads.

Ready to Accelerate the Future of AI?

If you're passionate about architecting AI acceleration cores from the ISA up — turning AI workloads into custom vector and matrix silicon — we'd love to hear from you.