Staff Hardware Board Design Engineer

Client of Gateworth Group; Dubai; On-site; AED 300,000 - 600,000; Full time

Job summary

Gateworth Group client seeks a senior hardware design engineer to lead board level high-speed design for accelerator cards, owning schematic and architecture for PCIe Gen4+/5/6 and memory interfaces. You will bring up ASIC/SoC, define stackups, design PDN/VRMs, and drive cross-functional debug with firmware and silicon teams.

Expertise with lab instruments (oscilloscopes, VNAs, BERTs), Python for automation, and a track record from concept to volume production, including DFM/DFT and ECO

Qualifications

• Board level high-speed digital design experience required.
• MUST have direct schematic and architecture ownership in last 3 years.
• Experience with Allegro System Capture, OrCAD/Altium or Xpedition.
• End-to-end ownership from concept through volume production with one platform.

Responsibilities

• Lead board level architecture and schematic ownership for accelerator cards and test platforms.
• Drive first silicon bring up, power on characterization, and cross-functional debug.
• Define stackup materials, impedance targets, and routing for PCIe Gen4+/5/6, DDR5/LPDDR5/9
• Oversee DFM/DFT/DFA, ECOs, BOM control, and vendor engagement during fabrication.

Skills

High speed digital design

Architecture ownership

End-to-end ownership

Lab automation

Python scripting

Education

Bachelor's degree in Electrical Engineering

Tools

Oscilloscopes

VNAs

BERTs

Protocol analyzers

Power analyzers

Job description

Main Responsibilities

Lead board level architecture and schematic ownership for accelerator cards modules and test platforms Design evaluation and bring up hardware for new ASICs SoCs including power rails sensing clocking access ports and instrumentation points Define stackup materials impedance targets and routing constraints for PCIe Gen4 5 6 DDR5 LPDDR5 GDDR and 25G SerDes interfaces Architect high current PDNs and multi phase VRMs at hundreds of amps including sequencing telemetry and decoupling strategy Drive first silicon bring up power on characterization margining and cross functional debug across hardware firmware and silicon Use lab instrumentation such as oscilloscopes high bandwidth probes VNAs BERTs protocol analyzers power analyzers and thermal tools Apply Python for lab automation data capture and measurement workflows Oversee DFM DFT DFA prototype builds ECOs BOM control and vendor engagement through fabrication and assembly Act as design authority in reviews producing clear documentation test plans and alignment across silicon firmware mechanical and manufacturing teams

Qualifications

Qualifications10 years of board level high speed digital design experience Direct schematic and architecture ownership within the last 3 years in Allegro System Capture OrCAD Altium or Xpedition One platform personally owned end to end from concept through volume production One first silicon bring up where you designed the board powering up a new ASIC SoC Hands on experience defining stackup and routing constraints for PCIe Gen4 DDR5 LPDDR5 GDDR or 25G SerDes Strong PDN and multi phase VRM design at high current levels including PMBus and sequencing Proficiency with lab instruments oscilloscopes VNAs BERTs protocol analyzers power analyzers thermal tools Python scripting for lab automation and measurement processing Solid understanding of DFM DFT DFA and manufacturing processes

Im afraid you would not be suitable for this role if you have Program or system leads managing ODM executed designs Engineers whose hands on design ended before 2020 Sustaining validation or test engineers without board architecture ownership

10+ years of board level high speed digital design experience. Direct schematic and architecture ownership within the last 3 years in Allegro System Capture, OrCAD/Altium, or Xpedition. One platform personally owned end to end from concept through volume production. One first silicon bring up where you designed the board powering up a new ASIC/SoC. Hands on experience defining stackup and routing constraints for PCIe Gen4+, DDR5, LPDDR5, GDDR, or 25G+ SerDes. Strong PDN and multi phase VRM design at high current levels, including PMBus and sequencing. Proficiency with lab instruments (oscilloscopes, VNAs, BERTs, protocol analyzers, power analyzers, thermal tools). Python scripting for lab automation and measurement processing. Solid understanding of DFM, DFT, DFA, and manufacturing processes.Im afraid you would not be suitable for this role if you have:Program or system leads managing ODM executed designs.Engineers whose hands on design ended before ~2020.Sustaining, validation, or test engineers without board architecture ownership.