Mixed-Signal Verification Engineer

Apple Inc.; Austin (TX); On-site; USD 139,000 - 257,000; Full time

Benefits offered by this job

Medical and dental coverage

Retirement benefits

Discounted products and services

Education expense reimbursement

Bonuses or commissions

Relocation assistance

Job summary

Apple Inc. in Austin is seeking a Mixed-Signal Verification Engineer to verify RF/Mixed-Signal blocks and SOCs, building testbenches and models in SystemVerilog within a UVM framework.

You will develop verification plans, run constrained tests, and debug issues across RF/Analog domains while collaborating with a multi-disciplinary team.

Qualifications

• BS and 3+ years of relevant industry experience.
• Experience verifying RF/Mixed-Signal blocks and SOCs.
• Expertise building Mixed-Signal testbenches, checkers and tests using System Verilog.
• Expertise creating and using real-numbered analog behavioral models in System Verilog/Verilog-AMS.
• Experience in HVL methodology (UVM/OVM/VMM) and HDL (System Verilog, Verilog).
• Strong verification skills in problem solving, constrained random testing and debugging.
• Understanding of common analog/RF blocks.
• Experience with signal processing using Python or Matlab a plus.
• Experience with Virtuoso Composer ADE and HED a plus.
• Team spirit excellent communication skills and the desire to take on diverse challenges.

Responsibilities

• Review specifications, extract features, define and execute verification plan.
• Develop top/block level Mixed Signal and Digital testbench and generate directed/ constrained random tests in a UVM framework.
• Build and reuse real numbered analog behavioral models, monitors and checkers for RF/Mixed-Signal blocks.
• Debug failures, fix testbench/model/checker issues, manage bug tracking and analyze and close coverage.
• Write scripts for automation of flow.
• Improve Mixed Signal verification methodology.

Skills

SystemVerilog

Verilog-AMS

UVM/OVM/VMM

Python

MATLAB

Analog/RF knowledge

Debugging

Constrained random testing

Communication

HVL methodology

Education

BS in Electrical Engineering

Tools

SystemVerilog

Verilog

URM/UVM tooling

Python

MATLAB

Virtuoso Composer ADE

HED

Job description

Mixed-Signal Verification Engineer

Posted: Dec 20 2023. Role Number: 200529910.

Would you like to join Apple’s growing wireless silicon development team? Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation Design Verification Test and Validation, and FW/SW engineering. In this role you will be verifying RF/Mixed-Signal blocks and SOCs using SystemVerilog to create testbenches, checkers, models and tests. You will build and execute test plans to meet project schedule and metric requirements including coverage metrics.

Key Qualifications

• BS and 3+ years of relevant industry experience.
• Industry verification experience with RF/Mixed-Signal blocks and SOCs.
• Expertise building Mixed-Signal testbenches, checkers and tests using System Verilog.
• Expertise creating and using real-numbered analog behavioral models in System Verilog/Verilog-AMS.
• Experience in HVL methodology (UVM/OVM/VMM) and HDL (System Verilog, Verilog) for verification.
• Strong verification skills in problem solving, constrained random testing and debugging.
• Understanding of common analog/RF blocks.
• Experience with signal processing using Python or Matlab a plus.
• Experience with Virtuoso Composer ADE and HED a plus.
• Team spirit excellent communication skills and the desire to take on diverse challenges.

Description

• Review specifications, extract features, define and execute verification plan.
• Develop top/block level Mixed Signal and Digital testbench and generate directed/ constrained random tests in a UVM framework.
• Build and reuse real numbered analog behavioral models, monitors and checkers for RF/Mixed-Signal blocks.
• Debug failures, fix testbench/model/checker issues, manage bug tracking and analyze and close coverage.
• Write scripts for automation of flow.
• Improve Mixed Signal verification methodology.

Education & Experience

BS and 3+ years of relevant industry experience.

Additional Requirements

Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants including minorities women protected veterans and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about disclose or discuss their compensation or that of other applicants.

Pay & Benefits

At Apple base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $138900 and $256500 and your base pay will depend on your skills qualifications experience and location. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan.

• Comprehensive medical and dental coverage
• retirement benefits
• a range of discounted products and free services
• reimbursement for certain educational expenses — including tuition
• discretionary bonuses or commission payments
• relocation