VP Hardware Engineering

BlueSteps Connect; United States; On-site; USD 250,000 - 500,000; Full time

Job summary

BlueSteps Connect seeks a VP Hardware Engineering to lead the end-to-end chip program for a purpose-built, low-latency AI inference accelerator. You will guide architecture through post-silicon bring-up and translate it into a scalable ASIC implementation in a fast-moving startup environment.

You will own the silicon lifecycle, mentor a high-performance hardware team across design, verification, and manufacturing, and partner with AI and software groups to optimize throughput and latency for LLM

Qualifications

• 10+ years of experience designing high-performance custom silicon for compute-intensive workloads.
• At least one successful tape-out in a leadership capacity.
• Strong knowledge of SoC/ASIC architecture, RTL and verification methodologies, physical design, and DFT.
• Experience converting FPGA prototypes into production silicon is highly valued.
• Proven ability to recruit, develop, and lead multidisciplinary teams and communicate complex trade-offs to executive and non-technical stakeholders.

Responsibilities

• Lead end-to-end chip program for a purpose-built, low-latency AI inference accelerator.
• Define architectural vision for a data-center-class inference accelerator and translate into scalable ASIC implementation.
• Own the silicon lifecycle: RTL design, verification, physical design, tape-out, and post-silicon validation.
• Build and mentor a high-performance hardware engineering organization across digital design, verification, physical implementation, packaging, and systems.
• Partner with applied-AI and software teams to optimize throughput and minimize latency for LLM workloads; work with foundries, EDA vendors, and manufacturing partners.

Skills

SoC/ASIC architecture

RTL design

Verification methodologies

Physical design

DFT

Memory hierarchies

High-bandwidth interconnects

Power-performance trade-offs

Team leadership

Job description

As VP Hardware Engineering, you will lead the end-to-end chip program for a purpose-built, low-latency AI inference accelerator, guiding architecture through post-silicon bring-up. You will define the architectural vision for a data-center-class inference accelerator and translate it into a scalable ASIC implementation, setting ambitious but achievable technical direction in a fast-moving, startup environment.

You will own the silicon lifecycle, including RTL design, verification, physical design, tape-out, and post-silicon validation. You will build and mentor a high-performance hardware engineering organization across digital design, verification, physical implementation, packaging, and systems, and partner closely with applied-AI and software teams to support hardware-software co-design that optimizes throughput and minimizes latency for LLM workloads. You will also work with foundries, EDA vendors, and manufacturing partners to drive technical diligence, risk reduction, and executive alignment.

To be successful, you should have 10+ years of experience designing high-performance custom silicon for compute-intensive workloads, including at least one successful tape-out in a leadership capacity. You should have strong knowledge of SoC/ASIC architecture, RTL and verification methodologies, physical design, and DFT, as well as familiarity with memory hierarchies and high-bandwidth interconnects and accelerator-class power-performance trade-offs. Experience converting FPGA prototypes into production silicon is highly valued, along with proven ability to recruit, develop, and lead multidisciplinary teams and communicate complex trade-offs clearly to executive and non-technical stakeholders.