VLSI CAD Engineer

Apple; Cupertino (CA); On-site; USD 149,000 - 195,000; Full time

Benefits offered by this job

Stock programs

Education reimbursement

Relocation assistance

Medical and dental coverage

Employee stock purchase plan

Job summary

Apple Inc. in Cupertino, CA, seeks a Senior SoC Synthesis Engineer to optimize synthesis flows and validate production-ready designs. You will work with Cadence Genus, PnR methodologies, and RTL analysis to enhance Power, Performance, and Area.

The role emphasizes automation through Python scripting, cross-functional collaboration, and ongoing feature validation for Apple silicon designs.

Qualifications

• Master's degree in Electrical Engineering or related field.
• Experience with synthesis EDA tools, CAD tool troubleshooting, and achieving timing closure.
• Proficiency in scripting for synthesis flow automation.
• Experience with SoC methodology, PnR experimentation, and design validation.
• Experience using RTL design analysis to evaluate metrics and correlations.
• Familiar with PPA optimization and post-synthesis verification.

Responsibilities

• Improve synthesis flow and resolve CAD tool issues to achieve timing closure.
• Automate synthesis workflows with scripting to streamline processes.
• Run PnR experiments and validate design features for production readiness.
• Analyze RTL against metrics and ensure post-synthesis correlation accuracy.
• Collaborate with LEQ and cross-functional teams to validate new features.

Skills

Synthesis flow automation

RTL design analysis

PPA optimization

Python scripting

EDA tool troubleshooting

SoC methodology

PnR experience

LEC validation

Education

Master's degree in Electrical Engineering

Tools

Cadence Genus

Genus scripting

Job description

Summary

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA.

• Support and enhance the Apple synthesis flow by optimizing processes and resolving any CAD tool issues that arise during the synthesis of System-on-Chip (SoC) partitions
• Work with industry-standard Electronic Design Automation (EDA) tools such as Cadence Genus and leveraging the Tel scripting language to fine-tune the synthesis flow, ensuring efficient and robust design implementation
• Engage in a proactive approach to troubleshooting, debugging, and refining synthesis methodologies to maintain seamless functionality within the Apple silicon design framework
• Validate and improving features that contribute to Power, Performance, and Area (PPA) enhancements
• Collaborate with the vendor team to refine and optimize these features, aligning them with the unique requirements of Apple silicon
• Perform an in-depth analysis of how each feature impacts PPA metrics, allowing for the identification of optimization opportunities
• Perform continuous monitoring and evaluation of the effectiveness of these enhancements, which help ensure that Apple's synthesis and design methodologies remain efficient and tailored to the evolving needs of high-performance SoC designs
• Conduct Synthesis and Place-and-Route (PnR) experiments on various SoC partitions to assess and validate new design features before incorporating them into production workflows
• Leverage a strong understanding of Register Transfer Level (RTL) design and an analytical approach to evaluating the effects of different plugins and attributes on design metrics
• Extend synthesis experiments through the PnR stage, which ensures that the correlation of Power, Performance, and Area (PPA) remains consistent across different design phases
• Ensure the post-synthesis and post-PnR results are well-aligned, which leads to an accurate and efficient implementation in final production-ready designs
• Collaborate with cross-functional teams, such as the Logic Equivalence (LEQ) team, to validate new features after synthesis
• Ensure the synthesized design maintains logical equivalence with the original RTL
• Develop automation scripts using Python to further streamline the synthesis workflow, which significantly reduces manual intervention and improves overall productivity

40 hours/week.

At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $148,987 - $194,700/yr and your base pay will depend on your skills, qualifications, experience, and location.

Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

Master’s degree or foreign equivalent in Electrical Engineering or related field.

• Using synthesis EDA tool, EDA tool optimization, and CAD tool troubleshooting to achieve timing closure, resolve quality-of-results issues, and improve design convergence across multiple process nodes
• Utilizing scripting languages for synthesis flow automation, including fine-tuning design implementation workflows
• Using scripting tools for automation development, including creating utilities and streamlining synthesis workflows
• Experience with System-on-Chip (SoC) methodology, Place-and-Route (PnR) experimentation, and validation of design features to verify physical implementation feasibility, ensure design integrity, and optimize floor planning strategies
• Using Register Transfer Level (RTL) design analysis to evaluate design metrics and correlation analysis
• Utilizing Power, Performance, and Area (PPA) optimization, feature validation, and enhancing automation flows to meet product specifications, reduce power consumption, and maximize performance within area constraints
• Using Logic Equivalence Checking (LEC) validation methods and cross-functional collaboration for design verification
• Using post-synthesis and post-PnR correlation analysis to ensure accuracy in production-ready designs
• Utilizing synthesis methodology development and refinement for proactive troubleshooting and debugging approach

Preferred Qualifications

N/A