FE Engineer

Apple Inc.; Cupertino (CA); On-site; USD 150,000 - 225,000; Full time

Benefits offered by this job

Medical and dental coverage

Employee stock purchase plan

Relocation assistance

Education reimbursement

Job summary

Apple Inc. in Cupertino, California, is seeking an experienced hardware RTL design engineer.

You will work with leads and architecture teams to define microarchitecture and develop RTL blocks using SystemVerilog/Verilog, integrating IPs and optimizing for timing, power, and performance. You will contribute through front-end synthesis/STA, timing closure, and collaboration across multidisciplinary groups to ensure on-time delivery and high-quality silicon.

Qualifications

• Master’s degree or foreign equivalent in Electrical Engineering or related field with 2 years of experience.
• 2 years of experience with SystemVerilog/Verilog RTL for CPU-based SoCs.
• Experience with CDC tools/techniques and multi-clock domains.
• RTL design experience with AMBA protocols (AHB).
• Experience with industry-standard simulation tools to verify/debug SoC or IP blocks.
• Configuring/integrating digital and analog IPs into an SoC/sub-system.
• Analyzing timing and resolving timing violations at digital-analog interfaces.
• Using lint tools to ensure RTL coding meets industry guidelines.
• Validating and debugging system silicon during chip bring-up.

Responsibilities

• Define the design microarchitecture with leads and architecture teams.
• Develop RTL design of blocks following architecture spec.
• Own RTL development/design and integrate shared IP blocks.
• Optimize memories and hard macros for the block.
• Complete front-end synthesis/STA to meet timing.
• Collaborate with multidisciplinary groups to ensure timely, high-quality delivery.
• Support timing, power, and performance optimization throughout the flow.
• Note: relocation may be available.

Skills

SystemVerilog / Verilog RTL

CDC tools / clock-domain techniques

AMBA / AHB RTL design

industry-standard simulation tools

digital and analog IP integration

timing analysis / STA

RTL linting standards

chip bring-up debugging

Education

Master’s degree in Electrical Engineering

Tools

SystemVerilog

Verilog

Job description

Cupertino, California, United States Hardware

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work with leads and architecture teams to define the design microarchitecture. Develop RTL design of one or more blocks following established design guidelines based on microarchitecture spec. Own all aspects of RTL development design. Work and collaborate with other designers in the group to deliver results. Integrate common/shared IP blocks and optimize memories/hard macros required for the block. Complete front-end synthesis/STA to ensure timing for the block is met. Optimize power/performance. Collaborate with multi-disciplinary groups to make sure designs are delivered on time and of the highest quality by incorporating proper checks at every stage of the design process. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html. Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.

Minimum Qualifications

• Master’s degree or foreign equivalent in Electrical Engineering or related field and 2 years of experience in the job offered or related occupation.
• 2 years of experience with each of the following skills is required:
• Utilizing System Verilog or Verilog to write RTL for CPU-based SoCs.
• Utilizing CDC tools/techniques and knowledge of multiple clock domains to fix the issues.
• Experience in RTL Design with AMBA protocols, such as AHB.
• Utilizing industry standard simulation tools to verify and debug functional behavior of an SoC or IP block-level design.
• Configuring and integrating digital and analog IPs into an SoC/sub-system.
• Analyzing timing and resolving timing violations at digital-analog interfaces.
• Utilizing LINT tools to ensure RTL coding meets industry guidelines.
• Validating and debugging system silicon functionality during chip bring-up.

Preferred Qualifications

• N/A

This position is not subject to the application limits.

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Apple accepts applications to this posting on an ongoing basis.