Verification Engineer 4

TekWissen LLC; Austin (TX); On-site; USD 90,000 - 150,000; Full time

Job summary

TekWissen Group in Austin, TX is seeking a Verification Engineer 4 for a 12-month onsite assignment. You will apply formal verification to complex semiconductor designs, writing properties with SystemVerilog Assertions and using FPV tools.

You will automate flows with TCL/Python/Perl and collaborate with design teams to improve coverage, constraints, and debug capabilities for robust silicon validation.

Qualifications

• Hands-on verification experience with formal methods.
• Proficiency in SystemVerilog Assertions (SVA).
• Experience with FPV, connectivity checking, register verification, equivalence checking, and coverage analysis.
• Scripting skills (TCL, Python, Perl) to automate flows.
• Strong focus on formal verification and SV/UVM is a plus.

Responsibilities

• Verify designs using formal verification methods across blocks.
• Develop test plans and properties using SVA and UVM.
• Automate verification flows with TCL/Python/Perl scripts.
• Analyze coverage and report verification results.

Skills

SVA (SystemVerilog Assertions)

Formal verification FPV

Connectivity checking

Register verification

Equivalence checking

Coverage analysis

Python/TCL/Perl scripting

Tools

VC Formal (Synopsys)

Jasper Gold (Cadence)

Job description

Overview

TekWissen is a global workforce management provider headquartered in Ann Arbor, Michigan that offers strategic talent solutions tour clients worldwide. This Client is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. Global company that specializes in manufacturing semiconductor devices used in computer processing. The company alsproduces flash memories, graphics processors, motherboard chip sets, and a variety of components used in consumer electronics goods.

Job Title: Verification Engineer 4

Work Location: Austin, TX 78735

Duration: 12 Months

Work Type: Temporary Assignment

Job Type: Onsite

Job Description

Preferred Experience

• Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence)


• Strong proficiency in System Verilog Assertions (SVA) and formal property specification


• Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis


• Familiarity with scripting languages (TCL, Python, Perl) for flow automation


• Extensive experience in design verification with a strong focus on formal verification


• Expertise in System Verilog and UVM-based verification methodologies - Nice to have

TekWissen Group is an equal opportunity employer supporting workforce diversity.