Verification Engineer IV — Formal Verification Expert

TekWissen LLC; Austin (TX); On-site; USD 90,000 - 150,000; Full time

Job summary

TekWissen Group in Austin, TX is seeking a Verification Engineer 4 for a 12-month onsite assignment. You will apply formal verification to complex semiconductor designs, writing properties with SystemVerilog Assertions and using FPV tools.

You will automate flows with TCL/Python/Perl and collaborate with design teams to improve coverage, constraints, and debug capabilities for robust silicon validation.

Qualifications

• Hands-on verification experience with formal methods.
• Proficiency in SystemVerilog Assertions (SVA).
• Experience with FPV, connectivity checking, register verification, equivalence checking, and coverage analysis.
• Scripting skills (TCL, Python, Perl) to automate flows.
• Strong focus on formal verification and SV/UVM is a plus.

Responsibilities

• Verify designs using formal verification methods across blocks.
• Develop test plans and properties using SVA and UVM.
• Automate verification flows with TCL/Python/Perl scripts.
• Analyze coverage and report verification results.

Skills

SVA (SystemVerilog Assertions)

Formal verification FPV

Connectivity checking

Register verification

Equivalence checking

Coverage analysis

Python/TCL/Perl scripting

Tools

VC Formal (Synopsys)

Jasper Gold (Cadence)

Job description

TekWissen Group in Austin, TX is seeking a Verification Engineer 4 for a 12-month onsite assignment. You will apply formal verification to complex semiconductor designs, writing properties with SystemVerilog Assertions and using FPV tools.

You will automate flows with TCL/Python/Perl and collaborate with design teams to improve coverage, constraints, and debug capabilities for robust silicon validation.